📄 toobin.c
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/***************************************************************************
Toobin Memory Map (preliminary)
-------------------------------
TOOBIN' 68010 MEMORY MAP
Function Address R/W DATA
-------------------------------------------------------------
Program ROM 000000-07FFFF R D0-D15
Playfield RAM C00000-C07FFF R/W D0-D15
Alphanumerics RAM C08000-C097FF R/W D0-D15
Motion Object RAM C09800-C09FFF R/W D0-D15
Color RAM Playfield C10000-C101FF R/W D0-D15
Color RAM Motion Object C10200-C103FF R/W D0-D15
Color RAM Alpha C10400-C105FF R/W D0-D15
Color RAM Extra? C10600-C107FF R/W D0-D15
???? (Dip switches?) FF6000 R
Watchdog reset FF8000-FF8001 W xx
68000-to-6502 data FF8101 W D0-D7
Video intensity (0=max, 1f=min) FF8300 W D0-D4
Scan line of next interrupt FF8340 W D0-D8
Head of motion object list FF8380 W D0-D7
Interrupt acknowledge FF83C0-FF83C1 W xx
Sound chip reset FF8400-FF8401 W D0
EEPROM output enable FF8500-FF8501 W xx
Horizontal scroll register FF8600-FF8601 W D6-D15
Vertical scroll register FF8700-FF8701 W D6-D15
Player 2 Throw FF8800-FF8801 R D9
Player 1 Throw R D8
Player 1 Paddle Forward (Right) R D7
Player 1 Paddle Forward (Left) R D6
Player 1 Paddle Backward (Left) R D5
Player 1 Paddle Backward (Right) R D4
Player 2 Paddle Forward (Right) R D3
Player 2 Paddle Forward (Left) R D2
Player 2 Paddle Backward (Left) R D1
Player 2 Paddle Backward (Right) R D0
VBLANK FF9000 R D14
Output buffer full (at FF8101) R D13
Self-test R D12
6502-to-68000 data FF9801 R D0-D7
EEPROM FFA000-FFAFFF R/W D0-D7
Program RAM FFC000-FFFFFF R/W D0-D15
TOOBIN' 6502 MEMORY MAP
Function Address R/W Data
---------------------------------------------------------------
Program RAM 0000-1FFF R/W D0-D7
Music (YM-2151) 2000-2001 R/W D0-D7
Read 68010 Port (Input Buffer) 280A R D0-D7
Self-test 280C R D7
Output Buffer Full (@2A02) (Active High) R D5
Left Coin Switch R D1
Right Coin Switch R D0
Interrupt acknowledge 2A00 W xx
Write 68010 Port (Outbut Buffer) 2A02 W D0-D7
Banked ROM select (at 3000-3FFF) 2A04 W D6-D7
??? 2A06 W
Effects 2C00-2C0F R/W D0-D7
Banked Program ROM (4 pages) 3000-3FFF R D0-D7
Static Program ROM (48K bytes) 4000-FFFF R D0-D7
****************************************************************************/
#include "driver.h"
#include "machine/atarigen.h"
#include "vidhrdw/generic.h"
#include "sndhrdw/pokey.h"
#include "sndhrdw/5220intf.h"
#include "sndhrdw/2151intf.h"
extern unsigned char *toobin_interrupt_scan;
extern unsigned char *toobin_intensity;
extern unsigned char *toobin_moslip;
int toobin_io_r (int offset);
int toobin_6502_switch_r (int offset);
int toobin_playfieldram_r (int offset);
int toobin_sound_r (int offset);
int toobin_controls_r (int offset);
void toobin_interrupt_scan_w (int offset, int data);
void toobin_interrupt_ack_w (int offset, int data);
void toobin_sound_reset_w (int offset, int data);
void toobin_moslip_w (int offset, int data);
void toobin_6502_bank_w (int offset, int data);
void toobin_paletteram_w (int offset, int data);
void toobin_playfieldram_w (int offset, int data);
int toobin_interrupt (void);
int toobin_sound_interrupt (void);
void toobin_init_machine (void);
int toobin_vh_start (void);
void toobin_vh_stop (void);
void toobin_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
/*************************************
*
* Main CPU memory handlers
*
*************************************/
static struct MemoryReadAddress toobin_readmem[] =
{
{ 0x000000, 0x07ffff, MRA_ROM },
{ 0xc00000, 0xc07fff, toobin_playfieldram_r },
{ 0xc08000, 0xc097ff, MRA_BANK2 },
{ 0xc09800, 0xc09fff, MRA_BANK3 },
{ 0xc10000, 0xc107ff, paletteram_word_r },
{ 0xff6000, 0xff6003, MRA_NOP }, /* who knows? read at controls time */
{ 0xff8800, 0xff8803, toobin_controls_r },
{ 0xff9000, 0xff9003, toobin_io_r },
{ 0xff9800, 0xff9803, atarigen_sound_r },
{ 0xffa000, 0xffafff, atarigen_eeprom_r },
{ 0xffc000, 0xffffff, MRA_BANK1 },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress toobin_writemem[] =
{
{ 0x000000, 0x07ffff, MWA_ROM },
{ 0xc00000, 0xc07fff, toobin_playfieldram_w, &atarigen_playfieldram, &atarigen_playfieldram_size },
{ 0xc08000, 0xc097ff, MWA_BANK2, &atarigen_alpharam, &atarigen_alpharam_size },
{ 0xc09800, 0xc09fff, MWA_BANK3, &atarigen_spriteram, &atarigen_spriteram_size },
{ 0xc10000, 0xc107ff, toobin_paletteram_w, &paletteram },
{ 0xff8000, 0xff8003, watchdog_reset_w },
{ 0xff8100, 0xff8103, atarigen_sound_w },
{ 0xff8300, 0xff8303, MWA_BANK7, &toobin_intensity },
{ 0xff8340, 0xff8343, toobin_interrupt_scan_w, &toobin_interrupt_scan },
{ 0xff8380, 0xff8383, toobin_moslip_w, &toobin_moslip },
{ 0xff83c0, 0xff83c3, toobin_interrupt_ack_w },
{ 0xff8400, 0xff8403, toobin_sound_reset_w },
{ 0xff8500, 0xff8503, atarigen_eeprom_enable_w },
{ 0xff8600, 0xff8603, MWA_BANK4, &atarigen_hscroll },
{ 0xff8700, 0xff8703, MWA_BANK5, &atarigen_vscroll },
{ 0xffa000, 0xffafff, atarigen_eeprom_w, &atarigen_eeprom, &atarigen_eeprom_size },
{ 0xffc000, 0xffffff, MWA_BANK1 },
{ -1 } /* end of table */
};
/*************************************
*
* Sound CPU memory handlers
*
*************************************/
static struct MemoryReadAddress toobin_sound_readmem[] =
{
{ 0x0000, 0x1fff, MRA_RAM },
{ 0x2000, 0x2001, YM2151_status_port_0_r },
{ 0x280a, 0x280a, atarigen_6502_sound_r },
{ 0x280c, 0x280c, toobin_6502_switch_r },
{ 0x280e, 0x280e, MRA_NOP },
{ 0x2c00, 0x2c0f, pokey1_r },
{ 0x3000, 0x3fff, MRA_BANK8 },
{ 0x4000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress toobin_sound_writemem[] =
{
{ 0x0000, 0x1fff, MWA_RAM },
{ 0x2000, 0x2000, YM2151_register_port_0_w },
{ 0x2001, 0x2001, YM2151_data_port_0_w },
{ 0x2a00, 0x2a00, MWA_NOP },
{ 0x2a02, 0x2a02, atarigen_6502_sound_w },
{ 0x2a04, 0x2a04, toobin_6502_bank_w },
{ 0x2a06, 0x2a06, MWA_NOP },
{ 0x2c00, 0x2c0f, pokey1_w },
{ 0x3000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
/*************************************
*
* Port definitions
*
*************************************/
INPUT_PORTS_START( toobin_ports )
PORT_START /* IN0 */
PORT_BIT( 0xfc, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
PORT_BITX(0x02, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2, "P2 Throw", OSD_KEY_COMMA, IP_JOY_DEFAULT, 0)
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
PORT_BITX(0x01, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1, "P1 Throw", OSD_KEY_LCONTROL, IP_JOY_DEFAULT, 0)
PORT_START /* IN1 */
PORT_BITX(0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1, "P1 Right Hand", OSD_KEY_E, IP_JOY_DEFAULT, 0)
PORT_BITX(0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1, "P1 Left Hand", OSD_KEY_Q, IP_JOY_DEFAULT, 0)
PORT_BITX(0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1, "P1 Left Foot", OSD_KEY_A, IP_JOY_DEFAULT, 0)
PORT_BITX(0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1, "P1 Right Foot", OSD_KEY_D, IP_JOY_DEFAULT, 0)
PORT_BITX(0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2, "P2 Right Hand", OSD_KEY_O, IP_JOY_DEFAULT, 0)
PORT_BITX(0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2, "P2 Left Hand", OSD_KEY_U, IP_JOY_DEFAULT, 0)
PORT_BITX(0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2, "P2 Left Foot", OSD_KEY_J, IP_JOY_DEFAULT, 0)
PORT_BITX(0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2, "P2 Right Foot", OSD_KEY_L, IP_JOY_DEFAULT, 0)
PORT_START /* IN2 */
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED ) /* self test */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) /* input buffer full */
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNUSED ) /* output buffer full */
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED ) /* speech chip ready */
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN3 )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
PORT_START /* DSW */
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_VBLANK )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BITX( 0x10, 0x10, IPT_DIPSWITCH_NAME | IPF_TOGGLE, "Self Test", OSD_KEY_F2, IP_JOY_NONE, 0 )
PORT_DIPSETTING( 0x10, "Off")
PORT_DIPSETTING( 0x00, "On")
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