📄 gladiatr.c
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case 0xe1: /* 8741-2,3 : ?? set parallelport mode ?? */
st->mode = GLADIATOR_8741_PORT;
st->parallelselect = 1; /* preset read number */
break;
case 0x62: /* 8741-3 : ? */
break;
case 0x4a: /* ?? syncronus with other cpu and return 00H */
st->pending_4a = 1;
if( st->mode == GLADIATOR_8741_MASTER )
{
sst = &gladiator_8741[st->connect];
/* release SLAVE command 4a holding */
if( sst->pending_4a )
{
sst->pending_4a = 0;
sst->rdata = 0x00; /* return code */
sst->status |= 0x01;
}
}
break;
case 0x80: /* 8741-3 : return check code */
st->rdata = 0x66;
st->status |= 0x01;
break;
case 0x81: /* 8741-2 : return check code */
st->rdata = 0x48;
st->status |= 0x01;
break;
}
}
/* Write data port */
void gladiator_8741_0_w(int offset, int data)
{
if(offset&1) I8741_command_w(0,data);
else I8741_data_w(0,data);
}
void gladiator_8741_1_w(int offset, int data)
{
if(offset&1) I8741_command_w(1,data);
else I8741_data_w(1,data);
}
void gladiator_8741_2_w(int offset, int data)
{
if(offset&1) I8741_command_w(2,data);
else I8741_data_w(2,data);
}
void gladiator_8741_3_w(int offset, int data)
{
if(offset&1) I8741_command_w(3,data);
else I8741_data_w(3,data);
}
/* read data port */
int gladiator_8741_0_r(int offset)
{
int ret;
if(offset&1) ret = I8741_status_r(0);
else ret = I8741_data_r(0);
return ret;
}
int gladiator_8741_1_r(int offset)
{
int ret;
if(offset&1) ret = I8741_status_r(1);
else ret = I8741_data_r(1);
return ret;
}
int gladiator_8741_2_r(int offset)
{
int ret;
if(offset&1) ret = I8741_status_r(2);
else ret = I8741_data_r(2);
return ret;
}
int gladiator_8741_3_r(int offset)
{
int ret;
if(offset&1) ret = I8741_status_r(3);
else ret = I8741_data_r(3);
return ret;
}
/*Sound Functions*/
void glad_adpcm_w( int channel, int data ) {
int command = data-0x03;
/*If sample # is 4,7,8 use the samples which playback at 5500Hz*/
if( command == 0x04 || command == 0x07 || command == 0x08)
sample_start(0,command==0x04?0:command==0x07?1:2,0);
else
ADPCM_trigger(0,command);
}
void glad_cpu_sound_command_w(int offset,int data)
{
soundlatch_w(0,data);
}
static struct MemoryReadAddress readmem[] =
{
{ 0x0000, 0x5fff, MRA_ROM },
{ 0x6000, 0x7fff, MRA_BANK1},
{ 0x8000, 0xbfff, MRA_BANK2},
{ 0xc000, 0xcbff, MRA_RAM },
{ 0xcc00, 0xcfff, gladiatr_video_registers_r },
{ 0xd000, 0xffff, MRA_RAM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress writemem[] =
{
{ 0x0000, 0xbfff, MWA_ROM },
{ 0xc000, 0xcbff, MWA_RAM, &spriteram },
{ 0xcc00, 0xcfff, gladiatr_video_registers_w },
{ 0xd000, 0xd1ff, gladiatr_paletteram_rg_w, &paletteram },
{ 0xd200, 0xd3ff, MWA_RAM },
{ 0xd400, 0xd5ff, gladiatr_paletteram_b_w, &paletteram_2 },
{ 0xd600, 0xd7ff, MWA_RAM },
{ 0xd800, 0xdfff, videoram_w, &videoram },
{ 0xe000, 0xe7ff, colorram_w, &colorram },
{ 0xe800, 0xefff, MWA_RAM, &gladiator_text },
{ 0xf000, 0xf3ff, MWA_RAM }, /* battery backed RAM */
{ 0xf400, 0xffff, MWA_RAM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress readmem_cpu2[] =
{
{ 0x0000, 0x3fff, MRA_ROM },
{ 0x8000, 0x83ff, MRA_RAM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress writemem_cpu2[] =
{
{ 0x0000, 0x3fff, MWA_ROM },
{ 0x8000, 0x83ff, MWA_RAM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress sound_readmem[] =
{
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress sound_writemem[] =
{
{ -1 } /* end of table */
};
static struct IOReadPort readport[] =
{
{ 0x02, 0x02, gladiatr_bankswitch_r },
{ 0x9e, 0x9f, gladiator_8741_0_r },
{ -1 } /* end of table */
};
static struct IOWritePort writeport[] =
{
{ 0x01, 0x01, gladiatr_spritebank_w},
{ 0x02, 0x02, gladiatr_bankswitch_w},
{ 0x04, 0x04, gladiatr_irq_patch_w}, /* !!! patch to 2nd CPU IRQ !!! */
{ 0x9e, 0x9f, gladiator_8741_0_w },
{ 0xbf, 0xbf, IORP_NOP },
{ -1 } /* end of table */
};
static struct IOReadPort readport_cpu2[] =
{
{ 0x00, 0x00, YM2203_status_port_0_r },
{ 0x01, 0x01, YM2203_read_port_0_r },
{ 0x20, 0x21, gladiator_8741_1_r },
{ 0x40, 0x40, IOWP_NOP },
{ 0x60, 0x61, gladiator_8741_2_r },
{ 0x80, 0x81, gladiator_8741_3_r },
{ -1 } /* end of table */
};
static struct IOWritePort writeport_cpu2[] =
{
{ 0x00, 0x00, YM2203_control_port_0_w },
{ 0x01, 0x01, YM2203_write_port_0_w },
{ 0x20, 0x21, gladiator_8741_1_w },
{ 0x60, 0x61, gladiator_8741_2_w },
{ 0x80, 0x81, gladiator_8741_3_w },
/* { 0x40, 0x40, glad_sh_irq_clr }, */
{ 0xe0, 0xe0, glad_adpcm_w },
{ -1 } /* end of table */
};
INPUT_PORTS_START( input_ports )
PORT_START /* DSW1 (8741-0 parallel port)*/
PORT_DIPNAME( 0x03, 0x01, "Difficulty", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Easy" )
PORT_DIPSETTING( 0x01, "Medium" )
PORT_DIPSETTING( 0x02, "Hard" )
PORT_DIPSETTING( 0x03, "Hardest" )
PORT_DIPNAME( 0x04, 0x04, "After 4 Stages", IP_KEY_NONE )
PORT_DIPSETTING( 0x04, "Continues" )
PORT_DIPSETTING( 0x00, "Ends" )
PORT_DIPNAME( 0x08, 0x00, "Bonus Life", IP_KEY_NONE ) /*NOTE: Actual manual has these settings reversed(typo?)! */
PORT_DIPSETTING( 0x00, "Only at 100000" )
PORT_DIPSETTING( 0x08, "Every 100000" )
PORT_DIPNAME( 0x30, 0x20, "Lives", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "1" )
PORT_DIPSETTING( 0x10, "2" )
PORT_DIPSETTING( 0x20, "3" )
PORT_DIPSETTING( 0x30, "4" )
PORT_DIPNAME( 0x40, 0x00, "Allow Continue", IP_KEY_NONE )
PORT_DIPSETTING( 0x40, "No" )
PORT_DIPSETTING( 0x00, "Yes" )
PORT_DIPNAME( 0x80, 0x80, "Demo Sounds", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x80, "On" )
PORT_START /* DSW2 (8741-1 parallel port) - Dips 6 Unused */
PORT_DIPNAME( 0x03, 0x00, "Coin A", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "1 Coin/1 Credit" )
PORT_DIPSETTING( 0x01, "1 Coin/2 Credits" )
PORT_DIPSETTING( 0x02, "1 Coin/4 Credits" )
PORT_DIPSETTING( 0x03, "1 Coin/5 Credits" )
PORT_DIPNAME( 0x0c, 0x00, "Coin B", IP_KEY_NONE )
PORT_DIPSETTING( 0x0c, "5 Coins/1 Credit" )
PORT_DIPSETTING( 0x08, "4 Coins/1 Credit" )
PORT_DIPSETTING( 0x04, "3 Coins/1 Credit" )
PORT_DIPSETTING( 0x00, "2 Coins/1 Credit" )
PORT_DIPNAME( 0x10, 0x00, "Free Play", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x10, "On" )
PORT_DIPNAME( 0x40, 0x40, "Cabinet", IP_KEY_NONE )
PORT_DIPSETTING( 0x40, "Upright" )
PORT_DIPSETTING( 0x00, "Cocktail" )
PORT_DIPNAME( 0x80, 0x00, "Flip Screen", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x80, "On" )
PORT_START /* DSW3 (YM2203 port B) - Dips 5,6,7 Unused */
PORT_BITX( 0x01, 0x00, IPT_DIPSWITCH_NAME | IPF_TOGGLE, "Invulnerability", IP_KEY_NONE, IP_JOY_NONE, 0 )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x01, "On" )
PORT_DIPNAME( 0x02, 0x00, "Memory Backup", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Normal" )
PORT_DIPSETTING( 0x02, "Clear" )
PORT_DIPNAME( 0x0c, 0x00, "Starting Stage", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "1" )
PORT_DIPSETTING( 0x04, "2" )
PORT_DIPSETTING( 0x08, "3" )
PORT_DIPSETTING( 0x0c, "4" )
PORT_BITX( 0x80, 0x00, IPT_DIPSWITCH_NAME | IPF_TOGGLE, "Service Mode", OSD_KEY_F2, IP_JOY_NONE, 0 )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x80, "On" )
PORT_START /* IN0 (8741-3 parallel port 1) */
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* COINS */
PORT_START /* COINS (8741-3 parallel port bit7) */
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START1 )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START2 )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BITX(0x40, IP_ACTIVE_HIGH, IPT_COIN1 | IPF_IMPULSE, "Coin A", IP_KEY_DEFAULT, IP_JOY_DEFAULT, 1)
PORT_BITX(0x80, IP_ACTIVE_HIGH, IPT_COIN2 | IPF_IMPULSE, "Coin B", IP_KEY_DEFAULT, IP_JOY_DEFAULT, 1)
PORT_START /* IN1 (8741-3 parallel port 2) */
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* COINS */
PORT_START /* IN2 (8741-3 parallel port 4) */
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_COCKTAIL )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_COCKTAIL )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_COCKTAIL )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* COINS */
PORT_START /* IN3 (8741-2 parallel port 1) */
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON3 )
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON3 | IPF_COCKTAIL )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
INPUT_PORTS_END
/*******************************************************************/
static struct GfxLayout gladiator_text_layout = /* gfxset 0 */
{
8,8, /* 8*8 tiles */
1024, /* number of tiles */
1, /* bits per pixel */
{ 0 }, /* plane offsets */
{ 0,1,2,3,4,5,6,7 }, /* x offsets */
{ 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 }, /* y offsets */
64 /* offset to next tile */
};
/*******************************************************************/
#define DEFINE_LAYOUT( NAME,P0,P1,P2) static struct GfxLayout NAME = { \
8,8,512,3, \
{ P0, P1, P2}, \
{ 0,1,2,3,64+0,64+1,64+2,64+3 }, \
{ 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 }, \
128 \
};
DEFINE_LAYOUT( gladiator_tile0, 4, 0x08000*8, 0x08000*8+4 )
DEFINE_LAYOUT( gladiator_tile1, 0, 0x0A000*8, 0x0A000*8+4 )
DEFINE_LAYOUT( gladiator_tile2, 4+0x2000*8, 0x10000*8, 0x10000*8+4 )
DEFINE_LAYOUT( gladiator_tile3, 0+0x2000*8, 0x12000*8, 0x12000*8+4 )
DEFINE_LAYOUT( gladiator_tile4, 4+0x4000*8, 0x0C000*8, 0x0C000*8+4 )
DEFINE_LAYOUT( gladiator_tile5, 0+0x4000*8, 0x0E000*8, 0x0E000*8+4 )
DEFINE_LAYOUT( gladiator_tile6, 4+0x6000*8, 0x14000*8, 0x14000*8+4 )
DEFINE_LAYOUT( gladiator_tile7, 0+0x6000*8, 0x16000*8, 0x16000*8+4 )
DEFINE_LAYOUT( gladiator_tileA, 4+0x2000*8, 0x0A000*8, 0x0A000*8+4 )
DEFINE_LAYOUT( gladiator_tileB, 0, 0x10000*8, 0x10000*8+4 )
DEFINE_LAYOUT( gladiator_tileC, 4+0x6000*8, 0x0E000*8, 0x0E000*8+4 )
DEFINE_LAYOUT( gladiator_tileD, 0+0x4000*8, 0x14000*8, 0x14000*8+4 )
static struct GfxDecodeInfo gfxdecodeinfo[] =
{
/* monochrome text layer */
{ 1, 0x34000, &gladiator_text_layout, 512, 1 },
/* background tiles */
{ 1, 0x18000, &gladiator_tile0, 0, 64 },
{ 1, 0x18000, &gladiator_tile1, 0, 64 },
{ 1, 0x18000, &gladiator_tile2, 0, 64 },
{ 1, 0x18000, &gladiator_tile3, 0, 64 },
{ 1, 0x18000, &gladiator_tile4, 0, 64 },
{ 1, 0x18000, &gladiator_tile5, 0, 64 },
{ 1, 0x18000, &gladiator_tile6, 0, 64 },
{ 1, 0x18000, &gladiator_tile7, 0, 64 },
/* sprites */
{ 1, 0x30000, &gladiator_tile0, 0, 64 },
{ 1, 0x30000, &gladiator_tileB, 0, 64 },
{ 1, 0x30000, &gladiator_tileA, 0, 64 },
{ 1, 0x30000, &gladiator_tile3, 0, 64 }, /* "GLAD..." */
{ 1, 0x00000, &gladiator_tile0, 0, 64 },
{ 1, 0x00000, &gladiator_tileB, 0, 64 },
{ 1, 0x00000, &gladiator_tileA, 0, 64 },
{ 1, 0x00000, &gladiator_tile3, 0, 64 }, /* ...DIATOR */
{ 1, 0x00000, &gladiator_tile4, 0, 64 },
{ 1, 0x00000, &gladiator_tileD, 0, 64 },
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