system8.c

这个是延伸mame的在wince平台下的游戏模拟器的代码

/******************************************************************************

Up'n Down, Mister Viking, Flicky, SWAT, Water Match and Bull Fight are known
to run on IDENTICAL hardware (they were sold by Bally-Midway as ROM swaps).

******************************************************************************/

#include "driver.h"
#include "vidhrdw/system8.h"
#include "z80/z80.h"

/* in machine/segacrpt.c */
void regulus_decode(void);
void mrviking_decode(void);
void swat_decode(void);
void flicky_decode(void);
void bullfgtj_decode(void);
void pitfall2_decode(void);
void nprinces_decode(void);
void seganinj_decode(void);
void imsorry_decode(void);
void teddybb_decode(void);
void hvymetal_decode(void);
void myheroj_decode(void);
void fdwarrio_decode(void);
void wboy3_decode(void);
void wboy4_decode(void);
void gardia_decode(void);



static void system8_init_machine(void)
{
	/* skip the long IC CHECK in Teddyboy Blues and Choplifter */
	/* this is not a ROM patch, the game checks a RAM location */
	/* before doing the test */
	Machine->memory_region[0][0xeffe] = 0x4f;
	Machine->memory_region[0][0xefff] = 0x4b;

	system8_define_sprite_pixelmode(SYSTEM8_SPRITE_PIXEL_MODE1);
	system8_define_background_memory(SYSTEM8_BACKGROUND_MEMORY_SINGLE);

	SN76496_set_clock(1,4000000);
}

static void chplft_init_machine(void)
{
	/* skip the long IC CHECK in Teddyboy Blues and Choplifter */
	/* this is not a ROM patch, the game checks a RAM location */
	/* before doing the test */
	Machine->memory_region[0][0xeffe] = 0x4f;
	Machine->memory_region[0][0xefff] = 0x4b;

	system8_define_sprite_pixelmode(SYSTEM8_SPRITE_PIXEL_MODE2);
	system8_define_background_memory(SYSTEM8_BACKGROUND_MEMORY_SINGLE);

	SN76496_set_clock(1,4000000);
}

static void wbml_init_machine(void)
{
	/* skip the long IC CHECK in Teddyboy Blues and Choplifter */
	/* this is not a ROM patch, the game checks a RAM location */
	/* before doing the test */
	Machine->memory_region[0][0xeffe] = 0x4f;
	Machine->memory_region[0][0xefff] = 0x4b;

	system8_define_sprite_pixelmode(SYSTEM8_SPRITE_PIXEL_MODE2);
	system8_define_background_memory(SYSTEM8_BACKGROUND_MEMORY_BANKED);

	SN76496_set_clock(1,4000000);
}


static int bankswitch;

int wbml_bankswitch_r(int offset)
{
	return bankswitch;
}

void hvymetal_bankswitch_w(int offset,int data)
{
	int bankaddress;
	unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];


	/* patch out the obnoxiously long startup RAM tests */
	ROM[0x4a55] = 0xc3;
	RAM[0x4a56] = 0xb6;
	RAM[0x4a57] = 0x4a;

	bankaddress = 0x10000 + (((data & 0x04)>>2) * 0x4000) + (((data & 0x40)>>5) * 0x4000);
	cpu_setbank(1,&RAM[bankaddress]);
	/* TODO: the memory system doesn't yet support bank switching on an encrypted */
	/* ROM, so we have to copy the data manually */
	memcpy(&ROM[0x8000],&RAM[bankaddress],0x4000);

	bankswitch = data;
}

void brain_bankswitch_w(int offset,int data)
{
	int bankaddress;
	unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];


	bankaddress = 0x10000 + (((data & 0x04)>>2) * 0x4000) + (((data & 0x40)>>5) * 0x4000);
	cpu_setbank(1,&RAM[bankaddress]);
	/* TODO: the memory system doesn't yet support bank switching on an encrypted */
	/* ROM, so we have to copy the data manually */
	memcpy(&ROM[0x8000],&RAM[bankaddress],0x4000);

	bankswitch = data;
}

void chplft_bankswitch_w(int offset,int data)
{
	int bankaddress;
	unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];


	bankaddress = 0x10000 + (((data & 0x0c)>>2) * 0x4000);
	cpu_setbank(1,&RAM[bankaddress]);

	bankswitch = data;
}

void wbml_bankswitch_w(int offset,int data)
{
	int bankaddress;
	unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];


	bankaddress = 0x10000 + (((data & 0x0c)>>2) * 0x4000);
	cpu_setbank(1,&RAM[bankaddress]);
	/* TODO: the memory system doesn't yet support bank switching on an encrypted */
	/* ROM, so we have to copy the data manually */
	if (ROM != RAM)
		memcpy(&ROM[0x8000],&RAM[bankaddress+0x20000],0x4000);

	bankswitch = data;
}

void system8_soundport_w(int offset, int data)
{
	soundlatch_w(0,data);
	cpu_cause_interrupt(1,Z80_NMI_INT);
}



static struct MemoryReadAddress readmem[] =
{
	{ 0x0000, 0xbfff, MRA_ROM },
	{ 0xc000, 0xefff, MRA_RAM },
	{ 0xf020, 0xf03f, MRA_RAM },
	{ 0xf800, 0xfbff, MRA_RAM },
	{ -1 } /* end of table */
};

static struct MemoryWriteAddress writemem[] =
{
	{ 0x0000, 0xbfff, MWA_ROM },
	{ 0xc000, 0xcfff, MWA_RAMROM },
	{ 0xd000, 0xd1ff, MWA_RAM, &spriteram, &spriteram_size },
	{ 0xd800, 0xdfff, system8_paletteram_w, &paletteram },
	{ 0xe000, 0xe7ff, system8_backgroundram_w, &system8_backgroundram, &system8_backgroundram_size },
	{ 0xe800, 0xeeff, MWA_RAM, &system8_videoram, &system8_videoram_size },
	{ 0xefbd, 0xefbd, MWA_RAM, &system8_scroll_y },
	{ 0xeffc, 0xeffd, MWA_RAM, &system8_scroll_x },
	{ 0xf000, 0xf3ff, system8_background_collisionram_w, &system8_background_collisionram },
	{ 0xf800, 0xfbff, system8_sprites_collisionram_w, &system8_sprites_collisionram },
	{ -1 } /* end of table */
};

static struct MemoryReadAddress wbml_readmem[] =
{
	{ 0x0000, 0x7fff, MRA_ROM },
	{ 0x8000, 0xbfff, MRA_BANK1 },
	{ 0xc000, 0xdfff, MRA_RAM },
	{ 0xe000, 0xefff, wbml_paged_videoram_r },
	{ 0xf020, 0xf03f, MRA_RAM },
	{ 0xf800, 0xfbff, MRA_RAM },
	{ -1 } /* end of table */
};

static struct MemoryWriteAddress wbml_writemem[] =
{
	{ 0x0000, 0xbfff, MWA_ROM },
	{ 0xc000, 0xcfff, MWA_RAMROM },
	{ 0xd000, 0xd1ff, MWA_RAM, &spriteram, &spriteram_size },
	{ 0xd800, 0xddff, system8_paletteram_w, &paletteram },
	{ 0xe000, 0xefff, wbml_paged_videoram_w },
	{ 0xf000, 0xf3ff, system8_background_collisionram_w, &system8_background_collisionram },
	{ 0xf800, 0xfbff, system8_sprites_collisionram_w, &system8_sprites_collisionram },
	{ -1 } /* end of table */
};

static struct MemoryReadAddress chplft_readmem[] =
{
	{ 0x0000, 0x7fff, MRA_ROM },
	{ 0x8000, 0xbfff, MRA_BANK1 },
	{ 0xc000, 0xefff, MRA_RAM },
	{ 0xf020, 0xf03f, MRA_RAM },
	{ 0xf800, 0xfbff, MRA_RAM },
	{ -1 } /* end of table */
};

static struct MemoryWriteAddress chplft_writemem[] =
{
	{ 0x0000, 0xbfff, MWA_ROM },
	{ 0xc000, 0xcfff, MWA_RAMROM },
	{ 0xd000, 0xd1ff, MWA_RAM, &spriteram, &spriteram_size },
	{ 0xd800, 0xdfff, system8_paletteram_w, &paletteram },
	{ 0xe7c0, 0xe7ff, choplifter_scroll_x_w, &system8_scrollx_ram },
	{ 0xe000, 0xe7ff, system8_videoram_w, &system8_videoram, &system8_videoram_size },
	{ 0xe800, 0xeeff, system8_backgroundram_w, &system8_backgroundram, &system8_backgroundram_size },
	{ 0xf000, 0xf3ff, system8_background_collisionram_w, &system8_background_collisionram },
	{ 0xf800, 0xfbff, system8_sprites_collisionram_w, &system8_sprites_collisionram },
	{ -1 } /* end of table */
};

static struct IOReadPort readport[] =
{
	{ 0x00, 0x00, input_port_0_r },	/* joy1 */
	{ 0x04, 0x04, input_port_1_r },	/* joy2 */
	{ 0x08, 0x08, input_port_2_r },	/* coin,start */
	{ 0x0c, 0x0c, input_port_3_r },	/* DIP2 */
	{ 0x0d, 0x0d, input_port_4_r },	/* DIP1 some games read it from here... */
	{ 0x10, 0x10, input_port_4_r },	/* DIP1 ... and some others from here */
									/* but there are games which check BOTH! */
	{ 0x15, 0x15, system8_videomode_r },
	{ 0x19, 0x19, system8_videomode_r },	/* mirror address */
	{ -1 }	/* end of table */
};

static struct IOWritePort writeport[] =
{
	{ 0x14, 0x14, system8_soundport_w },	/* sound commands */
	{ 0x15, 0x15, system8_videomode_w },	/* video control and (in some games) bank switching */
	{ 0x18, 0x18, system8_soundport_w },	/* mirror address */
	{ 0x19, 0x19, system8_videomode_w },	/* mirror address */
	{ -1 }	/* end of table */
};

static struct IOReadPort wbml_readport[] =
{
	{ 0x00, 0x00, input_port_0_r },	/* joy1 */
	{ 0x04, 0x04, input_port_1_r },	/* joy2 */
	{ 0x08, 0x08, input_port_2_r },	/* coin,start */
	{ 0x0c, 0x0c, input_port_3_r },	/* DIP2 */
	{ 0x0d, 0x0d, input_port_4_r },	/* DIP1 some games read it from here... */
	{ 0x10, 0x10, input_port_4_r },	/* DIP1 ... and some others from here */
									/* but there are games which check BOTH! */
	{ 0x15, 0x15, wbml_bankswitch_r },
	{ 0x16, 0x16, wbml_bg_bankselect_r },
	{ 0x19, 0x19, wbml_bankswitch_r },	/* mirror address */
	{ -1 }	/* end of table */
};

static struct IOWritePort wbml_writeport[] =
{
	{ 0x14, 0x14, system8_soundport_w },	/* sound commands */
	{ 0x15, 0x15, wbml_bankswitch_w },
	{ 0x16, 0x16, wbml_bg_bankselect_w },
	{ -1 }	/* end of table */
};

static struct IOWritePort hvymetal_writeport[] =
{
	{ 0x18, 0x18, system8_soundport_w },	/* sound commands */
	{ 0x19, 0x19, hvymetal_bankswitch_w },
	{ -1 }	/* end of table */
};

static struct IOWritePort brain_writeport[] =
{
	{ 0x18, 0x18, system8_soundport_w },	/* sound commands */
	{ 0x19, 0x19, brain_bankswitch_w },
	{ -1 }	/* end of table */
};

static struct IOWritePort chplft_writeport[] =
{
	{ 0x14, 0x14, system8_soundport_w },	/* sound commands */
	{ 0x15, 0x15, chplft_bankswitch_w },
	{ -1 }	/* end of table */
};


static struct MemoryReadAddress sound_readmem[] =
{
	{ 0x0000, 0x7fff, MRA_ROM },
	{ 0x8000, 0x87ff, MRA_RAM },
	{ 0xe000, 0xe000, soundlatch_r },
	{ -1 } /* end of table */
};

static struct MemoryWriteAddress sound_writemem[] =
{
	{ 0x0000, 0x7fff, MWA_ROM },
	{ 0x8000, 0x87ff, MWA_RAM },
	{ 0xa000, 0xa003, SN76496_0_w },	/* Choplifter writes to the four addresses */
	{ 0xc000, 0xc003, SN76496_1_w },	/* in sequence */
	{ -1 } /* end of table */
};


#define IN0_PORT \
	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) \
	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) \
	PORT_BITX(0x04, IP_ACTIVE_LOW, IPT_SERVICE, "Service Mode", OSD_KEY_F2, IP_JOY_NONE, 0 ) \
	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN3 ) \
	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 ) \
	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 ) \
	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )

#define DSW1_PORT \
	PORT_DIPNAME( 0x0f, 0x0f, "A Coin/Cred", IP_KEY_NONE ) \
	PORT_DIPSETTING(    0x07, "4/1" ) \
	PORT_DIPSETTING(    0x08, "3/1" ) \
	PORT_DIPSETTING(    0x09, "2/1" ) \
	PORT_DIPSETTING(    0x05, "2/1 + Bonus each 5" ) \
	PORT_DIPSETTING(    0x04, "2/1 + Bonus each 4" ) \
	PORT_DIPSETTING(    0x0f, "1/1" ) \
	PORT_DIPSETTING(    0x03, "1/1 + Bonus each 5" ) \
	PORT_DIPSETTING(    0x02, "1/1 + Bonus each 4" ) \
	PORT_DIPSETTING(    0x01, "1/1 + Bonus each 2" ) \
	PORT_DIPSETTING(    0x06, "2/3" ) \
	PORT_DIPSETTING(    0x0e, "1/2" ) \
	PORT_DIPSETTING(    0x0d, "1/3" ) \
	PORT_DIPSETTING(    0x0c, "1/4" ) \
	PORT_DIPSETTING(    0x0b, "1/5" ) \