📄 wc90.c
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/*
World Cup 90 ( Tecmo ) driver
-----------------------------
Ernesto Corvi
(ernesto@imagina.com)
CPU #1 : Handles background & foreground tiles, controllers, dipswitches.
CPU #2 : Handles sprites and palette
CPU #3 : Audio.
Memory Layout:
CPU #1
0000-8000 ROM
8000-9000 RAM
a000-a800 Color Ram for background #1 tiles
a800-b000 Video Ram for background #1 tiles
c000-c800 Color Ram for background #2 tiles
c800-c000 Video Ram for background #2 tiles
e000-e800 Color Ram for foreground tiles
e800-f000 Video Ram for foreground tiles
f800-fc00 Common Ram with CPU #2
fc00-fc00 Stick 1 input port
fc02-fc02 Stick 2 input port
fc05-fc05 Start buttons and Coins input port
fc06-fc06 Dip Switch A
fc07-fc07 Dip Switch B
CPU #2
0000-c000 ROM
c000-d000 RAM
d000-d800 RAM Sprite Ram
e000-e800 RAM Palette Ram
f800-fc00 Common Ram with CPU #1
CPU #3
0000-0xc000 ROM
???????????
Notes:
-----
Dip switches mapping is not complete. ( Anyone has the manual handy? )
Other than that, everything else seems to be complete.
*/
#include "driver.h"
#include "vidhrdw/generic.h"
#include "Z80/Z80.h"
extern unsigned char *wc90_shared;
extern unsigned char *wc90_tile_colorram, *wc90_tile_videoram;
extern unsigned char *wc90_tile_colorram2, *wc90_tile_videoram2;
extern unsigned char *wc90_scroll0xlo, *wc90_scroll0xhi;
extern unsigned char *wc90_scroll1xlo, *wc90_scroll1xhi;
extern unsigned char *wc90_scroll2xlo, *wc90_scroll2xhi;
extern unsigned char *wc90_scroll0ylo, *wc90_scroll0yhi;
extern unsigned char *wc90_scroll1ylo, *wc90_scroll1yhi;
extern unsigned char *wc90_scroll2ylo, *wc90_scroll2yhi;
extern int wc90_tile_videoram_size;
extern int wc90_tile_videoram_size2;
int wc90_vh_start( void );
void wc90_vh_stop( void );
int wc90_tile_videoram_r( int offset );
void wc90_tile_videoram_w( int offset, int v );
int wc90_tile_colorram_r( int offset );
void wc90_tile_colorram_w( int offset, int v );
int wc90_tile_videoram2_r( int offset );
void wc90_tile_videoram2_w( int offset, int v );
int wc90_tile_colorram2_r( int offset );
void wc90_tile_colorram2_w( int offset, int v );
int wc90_shared_r ( int offset );
void wc90_shared_w( int offset, int v );
void wc90_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
static void wc90_bankswitch_w( int offset,int data )
{
int bankaddress;
unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];
bankaddress = 0x10000 + ( ( data & 0xf8 ) << 8 );
cpu_setbank( 1,&RAM[bankaddress] );
}
static void wc90_bankswitch1_w( int offset,int data )
{
int bankaddress;
unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[1].memory_region];
bankaddress = 0x10000 + ( ( data & 0xf8 ) << 8 );
cpu_setbank( 2,&RAM[bankaddress] );
}
static void wc90_sound_command_w(int offset,int data)
{
soundlatch_w(offset,data);
cpu_cause_interrupt(2,Z80_NMI_INT);
}
static struct MemoryReadAddress wc90_readmem1[] =
{
{ 0x0000, 0x7fff, MRA_ROM },
{ 0x8000, 0x9fff, MRA_RAM }, /* Main RAM */
{ 0xa000, 0xa7ff, wc90_tile_colorram_r }, /* bg 1 color ram */
{ 0xa800, 0xafff, wc90_tile_videoram_r }, /* bg 1 tile ram */
{ 0xb000, 0xbfff, MRA_RAM },
{ 0xc000, 0xc7ff, wc90_tile_colorram2_r }, /* bg 2 color ram */
{ 0xc800, 0xcfff, wc90_tile_videoram2_r }, /* bg 2 tile ram */
{ 0xd000, 0xdfff, MRA_RAM },
{ 0xe000, 0xe7ff, colorram_r }, /* fg color ram */
{ 0xe800, 0xefff, videoram_r }, /* fg tile ram */
{ 0xf000, 0xf7ff, MRA_BANK1 },
{ 0xf800, 0xfbff, wc90_shared_r },
{ 0xfc00, 0xfc00, input_port_0_r }, /* Stick 1 */
{ 0xfc02, 0xfc02, input_port_1_r }, /* Stick 2 */
{ 0xfc05, 0xfc05, input_port_4_r }, /* Start & Coin */
{ 0xfc06, 0xfc06, input_port_2_r }, /* DIP Switch A */
{ 0xfc07, 0xfc07, input_port_3_r }, /* DIP Switch B */
{ -1 } /* end of table */
};
static struct MemoryReadAddress wc90_readmem2[] =
{
{ 0x0000, 0xbfff, MRA_ROM },
{ 0xc000, 0xcfff, MRA_RAM },
{ 0xd000, 0xd7ff, MRA_RAM },
{ 0xd800, 0xdfff, MRA_RAM },
{ 0xe000, 0xe7ff, MRA_RAM },
{ 0xf000, 0xf7ff, MRA_BANK2 },
{ 0xf800, 0xfbff, wc90_shared_r },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress wc90_writemem1[] =
{
{ 0x0000, 0x7fff, MWA_ROM },
{ 0x8000, 0x9fff, MWA_RAM },
{ 0xa000, 0xa7ff, wc90_tile_colorram_w, &wc90_tile_colorram },
{ 0xa800, 0xafff, wc90_tile_videoram_w, &wc90_tile_videoram, &wc90_tile_videoram_size },
{ 0xb000, 0xbfff, MWA_RAM },
{ 0xc000, 0xc7ff, wc90_tile_colorram2_w, &wc90_tile_colorram2 },
{ 0xc800, 0xcfff, wc90_tile_videoram2_w, &wc90_tile_videoram2, &wc90_tile_videoram_size2 },
{ 0xd000, 0xdfff, MWA_RAM },
{ 0xe000, 0xe7ff, colorram_w, &colorram },
{ 0xe800, 0xefff, videoram_w, &videoram, &videoram_size },
{ 0xf000, 0xf7ff, MWA_ROM },
{ 0xf800, 0xfbff, wc90_shared_w, &wc90_shared },
{ 0xfc02, 0xfc02, MWA_RAM, &wc90_scroll0ylo },
{ 0xfc03, 0xfc03, MWA_RAM, &wc90_scroll0yhi },
{ 0xfc06, 0xfc06, MWA_RAM, &wc90_scroll0xlo },
{ 0xfc07, 0xfc07, MWA_RAM, &wc90_scroll0xhi },
{ 0xfc22, 0xfc22, MWA_RAM, &wc90_scroll1ylo },
{ 0xfc23, 0xfc23, MWA_RAM, &wc90_scroll1yhi },
{ 0xfc26, 0xfc26, MWA_RAM, &wc90_scroll1xlo },
{ 0xfc27, 0xfc27, MWA_RAM, &wc90_scroll1xhi },
{ 0xfc42, 0xfc42, MWA_RAM, &wc90_scroll2ylo },
{ 0xfc43, 0xfc43, MWA_RAM, &wc90_scroll2yhi },
{ 0xfc46, 0xfc46, MWA_RAM, &wc90_scroll2xlo },
{ 0xfc47, 0xfc47, MWA_RAM, &wc90_scroll2xhi },
{ 0xfcc0, 0xfcc0, wc90_sound_command_w },
{ 0xfcd0, 0xfcd0, MWA_NOP }, /* ??? */
{ 0xfce0, 0xfce0, wc90_bankswitch_w },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress wc90_writemem2[] =
{
{ 0x0000, 0xbfff, MWA_ROM },
{ 0xc000, 0xcfff, MWA_RAM },
{ 0xd000, 0xd7ff, MWA_RAM, &spriteram, &spriteram_size },
{ 0xd800, 0xdfff, MWA_RAM },
{ 0xe000, 0xe7ff, paletteram_xxxxBBBBRRRRGGGG_swap_w, &paletteram },
{ 0xf000, 0xf7ff, MWA_ROM },
{ 0xf800, 0xfbff, wc90_shared_w },
{ 0xfc00, 0xfc00, wc90_bankswitch1_w },
{ 0xfc01, 0xfc01, MWA_NOP }, /* ??? */
{ -1 } /* end of table */
};
static struct MemoryReadAddress sound_readmem[] =
{
{ 0x0000, 0xbfff, MRA_ROM },
{ 0xf000, 0xf7ff, MRA_RAM },
{ 0xf800, 0xf800, YM2203_status_port_0_r },
{ 0xf801, 0xf801, YM2203_read_port_0_r },
{ 0xf802, 0xf802, YM2203_status_port_1_r },
{ 0xf803, 0xf803, YM2203_read_port_1_r },
{ 0xfc00, 0xfc00, MRA_NOP }, /* ??? adpcm ??? */
{ 0xfc10, 0xfc10, soundlatch_r },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress sound_writemem[] =
{
{ 0x0000, 0xbfff, MWA_ROM },
{ 0xf000, 0xf7ff, MWA_RAM },
{ 0xf800, 0xf800, YM2203_control_port_0_w },
{ 0xf801, 0xf801, YM2203_write_port_0_w },
{ 0xf802, 0xf802, YM2203_control_port_1_w },
{ 0xf803, 0xf803, YM2203_write_port_1_w },
{ -1 } /* end of table */
};
INPUT_PORTS_START( wc90_input_ports )
PORT_START /* IN0 bit 0-5 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* IN1 bit 0-5 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* DSWA */
PORT_DIPNAME( 0x0f, 0x0f, "Coinage", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "10 Coins/1 Credit" )
PORT_DIPSETTING( 0x08, "9 Coins/1 Credit" )
PORT_DIPSETTING( 0x04, "8 Coins/1 Credit" )
PORT_DIPSETTING( 0x0c, "7 Coins/1 Credit" )
PORT_DIPSETTING( 0x02, "6 Coins/1 Credit" )
PORT_DIPSETTING( 0x0a, "5 Coins/1 Credit" )
PORT_DIPSETTING( 0x06, "4 Coins/1 Credit" )
PORT_DIPSETTING( 0x0e, "3 Coins/1 Credit" )
PORT_DIPSETTING( 0x09, "2 Coins/1 Credit" )
PORT_DIPSETTING( 0x0f, "1 Coin/1 Credit" )
PORT_DIPSETTING( 0x01, "2 Coins/3 Credits" )
PORT_DIPSETTING( 0x07, "1 Coin/2 Credits" )
PORT_DIPSETTING( 0x0b, "1 Coin/3 Credits" )
PORT_DIPSETTING( 0x03, "1 Coin/4 Credits" )
PORT_DIPSETTING( 0x0d, "1 Coin/5 Credits" )
PORT_DIPSETTING( 0x05, "1 Coin/6 Credits" )
PORT_DIPNAME( 0x30, 0x30, "Difficulty", IP_KEY_NONE )
PORT_DIPSETTING( 0x30, "Easy" )
PORT_DIPSETTING( 0x10, "Normal" )
PORT_DIPSETTING( 0x20, "Hard" )
PORT_DIPSETTING( 0x00, "Hardest" )
PORT_DIPNAME( 0x40, 0x40, "Countdown Speed", IP_KEY_NONE )
PORT_DIPSETTING( 0x40, "Normal" )
PORT_DIPSETTING( 0x00, "Fast" )
PORT_DIPNAME( 0x80, 0x80, "Demo Sounds", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Off" )
PORT_DIPSETTING( 0x80, "On" )
PORT_START /* DSWB */
PORT_DIPNAME( 0x03, 0x03, "1 Player Game Time", IP_KEY_NONE )
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