📄 dec8.c
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else { cpu_setbank(3,&RAM[0x10000]); }
}
/******************************************************************************/
static void oscar_int_w(int offset, int data)
{
/* Deal with interrupts, coins also generate NMI to CPU 0 */
switch (offset) {
case 0: /* IRQ2 */
cpu_cause_interrupt (1, M6809_INT_IRQ);
return;
case 1: /* IRC 1 */
return;
case 2: /* IRQ 1 */
cpu_cause_interrupt (0, M6809_INT_IRQ);
return;
case 3: /* IRC 2 */
return;
}
}
/* Used by Shackled, Last Mission, Captain Silver */
static void shackled_int_w(int offset, int data)
{
switch (offset) {
case 0: /* CPU 2 - IRQ acknowledge */
return;
case 1: /* CPU 1 - IRQ acknowledge */
return;
case 2: /* i8751 - FIRQ acknowledge */
return;
case 3: /* IRQ 1 */
cpu_cause_interrupt (0, M6809_INT_IRQ);
return;
case 4: /* IRQ 2 */
cpu_cause_interrupt (1, M6809_INT_IRQ);
return;
}
}
/******************************************************************************/
static int dec8_share_r(int offset) { return dec8_shared_ram[offset]; }
static int dec8_share2_r(int offset) { return dec8_shared2_ram[offset]; }
static void dec8_share_w(int offset,int data) { dec8_shared_ram[offset]=data; }
static void dec8_share2_w(int offset,int data) { dec8_shared2_ram[offset]=data; }
static int shackled_sprite_r(int offset) { return spriteram[offset]; }
static void shackled_sprite_w(int offset,int data) { spriteram[offset]=data; }
static void shackled_video_w(int offset,int data) { videoram[offset]=data; }
static int shackled_video_r(int offset) { return videoram[offset]; }
/******************************************************************************/
static struct MemoryReadAddress cobra_readmem[] =
{
{ 0x0000, 0x0fff, MRA_RAM },
{ 0x1000, 0x1fff, dec8_video_r },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x2800, 0x2fff, MRA_RAM },
{ 0x3000, 0x31ff, paletteram_r },
{ 0x3800, 0x3800, input_port_0_r }, /* Player 1 */
{ 0x3801, 0x3801, input_port_1_r }, /* Player 2 */
{ 0x3802, 0x3802, input_port_3_r }, /* Dip 1 */
{ 0x3803, 0x3803, input_port_4_r }, /* Dip 2 */
{ 0x3a00, 0x3a00, input_port_2_r }, /* VBL & coins */
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress cobra_writemem[] =
{
{ 0x0000, 0x0fff, MWA_RAM },
{ 0x1000, 0x1fff, dec8_video_w },
{ 0x2000, 0x27ff, MWA_RAM, &videoram, &videoram_size },
{ 0x2800, 0x2fff, MWA_RAM, &spriteram },
{ 0x3000, 0x31ff, paletteram_xxxxBBBBGGGGRRRR_swap_w, &paletteram },
{ 0x3200, 0x37ff, MWA_RAM }, /* Unknown, seemingly unused */
{ 0x3800, 0x381f, dec8_bac06_0_w },
{ 0x3a00, 0x3a1f, dec8_bac06_1_w },
{ 0x3c00, 0x3c00, dec8_bank_w },
{ 0x3c02, 0x3c02, MWA_NOP }, /* DMA flag? */
{ 0x3e00, 0x3e00, dec8_sound_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress ghostb_readmem[] =
{
{ 0x0000, 0x1fff, MRA_RAM },
{ 0x2000, 0x27ff, dec8_video_r },
{ 0x2800, 0x2dff, MRA_RAM },
{ 0x3000, 0x37ff, MRA_RAM },
{ 0x3800, 0x3800, input_port_0_r }, /* Player 1 */
{ 0x3801, 0x3801, input_port_1_r }, /* Player 2 */
{ 0x3802, 0x3802, input_port_2_r }, /* Player 3 */
{ 0x3803, 0x3803, input_port_3_r }, /* Start buttons + VBL */
{ 0x3820, 0x3820, input_port_5_r }, /* Dip */
{ 0x3840, 0x3840, i8751_h_r },
{ 0x3860, 0x3860, i8751_l_r },
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress ghostb_writemem[] =
{
{ 0x0000, 0x0fff, MWA_RAM },
{ 0x1000, 0x17ff, MWA_RAM },
{ 0x1800, 0x1fff, MWA_RAM, &videoram },
{ 0x2000, 0x27ff, dec8_video_w },
{ 0x2800, 0x2bff, MWA_RAM }, /* Scratch ram for rowscroll? */
{ 0x2c00, 0x2dff, MWA_RAM, &dec8_row },
{ 0x2e00, 0x2fff, MWA_RAM }, /* Unused */
{ 0x3000, 0x37ff, MWA_RAM, &spriteram },
{ 0x3800, 0x3800, dec8_sound_w },
{ 0x3820, 0x3827, dec8_pf2_w },
{ 0x3830, 0x3833, dec8_scroll2_w },
{ 0x3840, 0x3840, ghostb_bank_w },
{ 0x3860, 0x3861, ghostb_i8751_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress srdarwin_readmem[] =
{
{ 0x0000, 0x13ff, MRA_RAM },
{ 0x1400, 0x17ff, dec8_video_r },
{ 0x2000, 0x2000, i8751_h_r },
{ 0x2001, 0x2001, i8751_l_r },
{ 0x3800, 0x3800, input_port_2_r }, /* Dip */
{ 0x3801, 0x3801, input_port_0_r }, /* Player */
{ 0x3802, 0x3802, input_port_1_r }, /* VBL */
{ 0x3803, 0x3803, input_port_3_r }, /* Dip */
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress srdarwin_writemem[] =
{
{ 0x0000, 0x05ff, MWA_RAM },
{ 0x0600, 0x07ff, MWA_RAM, &spriteram },
{ 0x0800, 0x0fff, MWA_RAM, &videoram },
{ 0x1000, 0x13ff, MWA_RAM },
{ 0x1400, 0x17ff, dec8_video_w },
{ 0x1800, 0x1801, srdarwin_i8751_w },
{ 0x1802, 0x1802, i8751_reset_w },
{ 0x1803, 0x1803, MWA_NOP }, /* NMI ack */
{ 0x1804, 0x1804, MWA_NOP }, /* DMA */
{ 0x1805, 0x1806, srdarwin_control_w }, /* Scroll & Bank */
{ 0x2000, 0x2000, dec8_sound_w }, /* Sound */
{ 0x2001, 0x2001, MWA_NOP }, /* Flipscreen (not supported) */
{ 0x2800, 0x288f, paletteram_xxxxBBBBGGGGRRRR_split1_w, &paletteram },
{ 0x3000, 0x308f, paletteram_xxxxBBBBGGGGRRRR_split2_w, &paletteram_2 },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress gondo_readmem[] =
{
{ 0x0000, 0x1fff, MRA_RAM },
{ 0x2000, 0x27ff, dec8_video_r },
{ 0x2800, 0x2fff, MRA_RAM },
{ 0x3000, 0x37ff, MRA_RAM }, /* Sprites */
{ 0x3800, 0x3800, input_port_7_r }, /* Dip 1 */
{ 0x3801, 0x3801, input_port_8_r }, /* Dip 2 */
{ 0x380a, 0x380b, gondo_player_1_r }, /* Player 1 rotary */
{ 0x380c, 0x380d, gondo_player_2_r }, /* Player 2 rotary */
{ 0x380e, 0x380e, input_port_3_r }, /* VBL */
{ 0x380f, 0x380f, input_port_2_r }, /* Fire buttons */
{ 0x3838, 0x3838, i8751_h_r },
{ 0x3839, 0x3839, i8751_l_r },
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress gondo_writemem[] =
{
{ 0x0000, 0x17ff, MWA_RAM },
{ 0x1800, 0x1fff, MWA_RAM, &videoram, &videoram_size },
{ 0x2000, 0x27ff, dec8_video_w },
{ 0x2800, 0x2bff, paletteram_xxxxBBBBGGGGRRRR_split1_w, &paletteram },
{ 0x2c00, 0x2fff, paletteram_xxxxBBBBGGGGRRRR_split2_w, &paletteram_2 },
{ 0x3000, 0x37ff, MWA_RAM, &spriteram },
{ 0x3810, 0x3810, dec8_sound_w },
{ 0x3818, 0x382f, gondo_scroll_w },
{ 0x3830, 0x3830, ghostb_bank_w }, /* Bank + NMI enable */
{ 0x383a, 0x383b, gondo_i8751_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress oscar_readmem[] =
{
{ 0x0000, 0x0eff, dec8_share_r },
{ 0x0f00, 0x0fff, MRA_RAM },
{ 0x1000, 0x1fff, dec8_share2_r },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x2800, 0x2fff, dec8_video_r },
{ 0x3000, 0x37ff, MRA_RAM }, /* Sprites */
{ 0x3800, 0x3bff, paletteram_r },
{ 0x3c00, 0x3c00, input_port_0_r },
{ 0x3c01, 0x3c01, input_port_1_r },
{ 0x3c02, 0x3c02, input_port_2_r }, /* VBL & coins */
{ 0x3c03, 0x3c03, input_port_3_r }, /* Dip 1 */
{ 0x3c04, 0x3c04, input_port_4_r },
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress oscar_writemem[] =
{
{ 0x0000, 0x0eff, dec8_share_w, &dec8_shared_ram },
{ 0x0f00, 0x0fff, MWA_RAM },
{ 0x1000, 0x1fff, dec8_share2_w, &dec8_shared2_ram },
{ 0x2000, 0x27ff, MWA_RAM, &videoram, &videoram_size },
{ 0x2800, 0x2fff, dec8_video_w },
{ 0x3000, 0x37ff, MWA_RAM, &spriteram },
{ 0x3800, 0x3bff, paletteram_xxxxBBBBGGGGRRRR_swap_w, &paletteram },
{ 0x3c10, 0x3c13, dec8_scroll2_w },
{ 0x3c80, 0x3c80, MWA_NOP }, /* DMA */
{ 0x3d00, 0x3d00, dec8_bank_w }, /* BNKS */
{ 0x3d80, 0x3d80, oscar_sound_w }, /* SOUN */
{ 0x3e00, 0x3e00, MWA_NOP }, /* COINCL */
{ 0x3e80, 0x3e83, oscar_int_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress oscar_sub_readmem[] =
{
{ 0x0000, 0x0eff, dec8_share_r },
{ 0x0f00, 0x0fff, MRA_RAM },
{ 0x1000, 0x1fff, dec8_share2_r },
{ 0x4000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress oscar_sub_writemem[] =
{
{ 0x0000, 0x0eff, dec8_share_w },
{ 0x0f00, 0x0fff, MWA_RAM },
{ 0x1000, 0x1fff, dec8_share2_w },
{ 0x3e80, 0x3e83, oscar_int_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress lastmiss_readmem[] =
{
{ 0x0000, 0x0fff, dec8_share_r },
{ 0x1000, 0x17ff, MRA_RAM },
{ 0x1800, 0x1800, input_port_0_r },
{ 0x1801, 0x1801, input_port_1_r },
{ 0x1802, 0x1802, input_port_2_r },
{ 0x1803, 0x1803, input_port_3_r }, /* Dip 1 */
{ 0x1804, 0x1804, input_port_4_r }, /* Dip 2 */
{ 0x1806, 0x1806, i8751_h_r },
{ 0x1807, 0x1807, i8751_l_r },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x2800, 0x2fff, MRA_RAM },
{ 0x3000, 0x37ff, dec8_share2_r },
{ 0x3800, 0x3fff, dec8_video_r },
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress lastmiss_writemem[] =
{
{ 0x0000, 0x0fff, dec8_share_w, &dec8_shared_ram },
{ 0x1000, 0x13ff, paletteram_xxxxBBBBGGGGRRRR_split1_w, &paletteram },
{ 0x1400, 0x17ff, paletteram_xxxxBBBBGGGGRRRR_split2_w, &paletteram_2 },
{ 0x1800, 0x1804, shackled_int_w },
{ 0x1805, 0x1805, MWA_NOP }, /* DMA */
{ 0x1807, 0x1807, MWA_NOP }, /* Flipscreen */
{ 0x1809, 0x1809, lastmiss_scrollx_w }, /* Scroll LSB */
{ 0x180b, 0x180b, lastmiss_scrolly_w }, /* Scroll LSB */
{ 0x180c, 0x180c, oscar_sound_w },
{ 0x180d, 0x180d, lastmiss_control_w }, /* Bank switch + Scroll MSB */
{ 0x180e, 0x180f, lastmiss_i8751_w },
{ 0x2000, 0x27ff, MWA_RAM, &videoram, &videoram_size },
{ 0x2800, 0x2fff, MWA_RAM, &spriteram },
{ 0x3000, 0x37ff, dec8_share2_w, &dec8_shared2_ram },
{ 0x3800, 0x3fff, dec8_video_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress lastmiss_sub_readmem[] =
{
{ 0x0000, 0x0fff, dec8_share_r },
{ 0x1800, 0x1800, input_port_0_r },
{ 0x1801, 0x1801, input_port_1_r },
{ 0x1802, 0x1802, input_port_2_r },
{ 0x1803, 0x1803, input_port_3_r }, /* Dip 1 */
{ 0x1804, 0x1804, input_port_4_r }, /* Dip 2 */
{ 0x3000, 0x37ff, dec8_share2_r },
{ 0x3800, 0x3fff, dec8_video_r },
{ 0x4000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress lastmiss_sub_writemem[] =
{
{ 0x0000, 0x0fff, dec8_share_w },
{ 0x1000, 0x13ff, paletteram_xxxxBBBBGGGGRRRR_split1_w },
{ 0x1400, 0x17ff, paletteram_xxxxBBBBGGGGRRRR_split2_w },
{ 0x1800, 0x1804, shackled_int_w },
{ 0x1805, 0x1805, MWA_NOP }, /* DMA */
{ 0x1807, 0x1807, MWA_NOP }, /* Flipscreen */
{ 0x180c, 0x180c, oscar_sound_w },
{ 0x2000, 0x27ff, shackled_video_w },
{ 0x2800, 0x2fff, shackled_sprite_w },
{ 0x3000, 0x37ff, dec8_share2_w },
{ 0x3800, 0x3fff, dec8_video_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress shackled_readmem[] =
{
{ 0x0000, 0x0fff, dec8_share_r },
{ 0x1000, 0x17ff, MRA_RAM },
{ 0x1800, 0x1800, input_port_0_r },
{ 0x1801, 0x1801, input_port_1_r },
{ 0x1802, 0x1802, input_port_2_r },
{ 0x1803, 0x1803, input_port_3_r },
{ 0x1804, 0x1804, input_port_4_r },
{ 0x2000, 0x27ff, shackled_video_r },
{ 0x2800, 0x2fff, shackled_sprite_r },
{ 0x3000, 0x37ff, dec8_share2_r },
{ 0x3800, 0x3fff, dec8_video_r },
{ 0x4000, 0x7fff, MRA_BANK1 },
{ 0x8000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress shackled_writemem[] =
{
{ 0x0000, 0x0fff, dec8_share_w, &dec8_shared_ram },
{ 0x1000, 0x13ff, paletteram_xxxxBBBBGGGGRRRR_split1_w, &paletteram },
{ 0x1400, 0x17ff, paletteram_xxxxBBBBGGGGRRRR_split2_w, &paletteram_2 },
{ 0x1800, 0x1804, shackled_int_w },
{ 0x1805, 0x1805, MWA_NOP }, /* DMA */
{ 0x1809, 0x1809, lastmiss_scrollx_w }, /* Scroll LSB */
{ 0x180b, 0x180b, lastmiss_scrolly_w }, /* Scroll LSB */
{ 0x180c, 0x180c, oscar_sound_w },
{ 0x180d, 0x180d, lastmiss_control_w }, /* Bank switch + Scroll MSB */
{ 0x2000, 0x27ff, shackled_video_w },
{ 0x2800, 0x2fff, shackled_sprite_w },
{ 0x3000, 0x37ff, dec8_share2_w, &dec8_shared2_ram },
{ 0x3800, 0x3fff, dec8_video_w },
{ 0x4000, 0xffff, MWA_ROM },
{ -1 } /* end of table */
};
static struct MemoryReadAddress shackled_sub_readmem[] =
{
{ 0x0000, 0x0fff, dec8_share_r },
{ 0x1000, 0x17ff, MRA_RAM },
{ 0x1800, 0x1800, input_port_0_r },
{ 0x1801, 0x1801, input_port_1_r },
{ 0x1802, 0x1802, input_port_2_r },
{ 0x1803, 0x1803, input_port_3_r },
{ 0x1804, 0x1804, input_port_4_r },
{ 0x1806, 0x1806, i8751_h_r },
{ 0x1807, 0x1807, i8751_l_r },
{ 0x2000, 0x27ff, MRA_RAM },
{ 0x2800, 0x2fff, MRA_RAM },
{ 0x3000, 0x37ff, dec8_share2_r },
{ 0x3800, 0x3fff, dec8_video_r },
{ 0x4000, 0xffff, MRA_ROM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress shackled_sub_writemem[] =
{
{ 0x0000, 0x0fff, dec8_share_w },
{ 0x1000, 0x13ff, paletteram_xxxxBBBBGGGGRRRR_split1_w, &paletteram },
{ 0x1400, 0x17ff, paletteram_xxxxBBBBGGGGRRRR_split2_w, &paletteram_2 },
{ 0x1800, 0x1804, shackled_int_w },
{ 0x1805, 0x1805, MWA_NOP }, /* DMA */
{ 0x1809, 0x1809, lastmiss_scrollx_w }, /* Scroll LSB */
{ 0x180b, 0x180b, lastmiss_scrolly_w }, /* Scroll LSB */
{ 0x180c, 0x180c, oscar_sound_w },
{ 0x180d, 0x180d, lastmiss_control_w }, /* Bank switch + Scroll MSB */
{ 0x180e, 0x180f, shackled_i8751_w },
{ 0x2000, 0x27ff, MWA_RAM, &videoram, &videoram_size },
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