📄 sidearms.c
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/***************************************************************************
Sidearms
========
Driver provided by Paul Leaman
There is an additional ROM which seems to contain code for a third Z80,
however the board only has two. The ROM is related to the missing star
background. At one point, the code jumps to A000, outside of the ROM
address space.
This ROM could be something entirely different from Z80 code. In another
set, it consists of only the second half of the one we have here.
***************************************************************************/
#include "driver.h"
#include "vidhrdw/generic.h"
extern unsigned char *sidearms_bg_scrollx,*sidearms_bg_scrolly;
extern unsigned char *sidearms_bg2_scrollx,*sidearms_bg2_scrolly;
void sidearms_c804_w(int offset, int data);
int sidearms_vh_start(void);
void sidearms_vh_stop(void);
void sidearms_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
void sidearms_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
static void sidearms_bankswitch_w(int offset,int data)
{
int bankaddress;
unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];
/* bits 0 and 1 select the ROM bank */
bankaddress = 0x10000 + (data & 0x0f) * 0x4000;
cpu_setbank(1,&RAM[bankaddress]);
}
static struct MemoryReadAddress readmem[] =
{
{ 0x0000, 0x7fff, MRA_ROM },
{ 0x8000, 0xbfff, MRA_BANK1 },
{ 0xc800, 0xc800, input_port_0_r },
{ 0xc801, 0xc801, input_port_1_r },
{ 0xc802, 0xc802, input_port_2_r },
{ 0xc803, 0xc803, input_port_3_r },
{ 0xc804, 0xc804, input_port_4_r },
{ 0xc805, 0xc805, input_port_5_r },
{ 0xd000, 0xffff, MRA_RAM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress writemem[] =
{
{ 0x0000, 0xbfff, MWA_ROM },
{ 0xc000, 0xc3ff, paletteram_xxxxBBBBRRRRGGGG_split1_w, &paletteram },
{ 0xc400, 0xc7ff, paletteram_xxxxBBBBRRRRGGGG_split2_w, &paletteram_2 },
{ 0xc800, 0xc800, soundlatch_w },
{ 0xc801, 0xc801, sidearms_bankswitch_w },
{ 0xc802, 0xc802, MWA_NOP }, /* watchdog reset? */
{ 0xc804, 0xc804, sidearms_c804_w },
{ 0xc805, 0xc805, MWA_RAM, &sidearms_bg2_scrollx },
{ 0xc806, 0xc806, MWA_RAM, &sidearms_bg2_scrolly },
{ 0xc808, 0xc809, MWA_RAM, &sidearms_bg_scrollx },
{ 0xc80a, 0xc80b, MWA_RAM, &sidearms_bg_scrolly },
{ 0xd000, 0xd7ff, videoram_w, &videoram, &videoram_size },
{ 0xd800, 0xdfff, colorram_w, &colorram },
{ 0xe000, 0xefff, MWA_RAM },
{ 0xf000, 0xffff, MWA_RAM, &spriteram, &spriteram_size },
{ -1 } /* end of table */
};
#ifdef THIRD_CPU
static void pop(int offset,int data)
{
RAM[0xa000] = 0xc3;
RAM[0xa001] = 0x00;
RAM[0xa002] = 0xa0;
}
static struct MemoryReadAddress readmem2[] =
{
{ 0x0000, 0x7fff, MRA_ROM },
{ 0xc000, 0xdfff, MRA_RAM },
{ 0xe000, 0xe3ff, MRA_RAM },
{ 0xe400, 0xe7ff, MRA_RAM },
{ 0xe800, 0xebff, MRA_RAM },
{ 0xec00, 0xefff, MRA_RAM },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress writemem2[] =
{
{ 0x0000, 0x7fff, MWA_ROM },
{ 0xc000, 0xdfff, MWA_RAM },
{ 0xe000, 0xe3ff, MWA_RAM },
{ 0xe400, 0xe7ff, MWA_RAM },
{ 0xe800, 0xebff, MWA_RAM },
{ 0xec00, 0xefff, MWA_RAM },
{ 0xf80e, 0xf80e, pop }, /* ROM bank selector? (to appear at 8000) */
{ -1 } /* end of table */
};
#endif
static struct MemoryReadAddress sound_readmem[] =
{
{ 0x0000, 0x7fff, MRA_ROM },
{ 0xc000, 0xc7ff, MRA_RAM },
{ 0xd000, 0xd000, soundlatch_r },
{ 0xf000, 0xf000, YM2203_status_port_0_r },
{ 0xf002, 0xf002, YM2203_status_port_1_r },
{ -1 } /* end of table */
};
static struct MemoryWriteAddress sound_writemem[] =
{
{ 0x0000, 0x7fff, MWA_ROM },
{ 0xc000, 0xc7ff, MWA_RAM },
{ 0xf000, 0xf000, YM2203_control_port_0_w },
{ 0xf001, 0xf001, YM2203_write_port_0_w },
{ 0xf002, 0xf002, YM2203_control_port_1_w },
{ 0xf003, 0xf003, YM2203_write_port_1_w },
{ -1 } /* end of table */
};
INPUT_PORTS_START( input_ports )
PORT_START /* IN0 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_DIPNAME( 0x08, 0x08, "Freeze", IP_KEY_NONE ) /* I don't think it's really a dip switch */
PORT_DIPSETTING( 0x08, "Off" )
PORT_DIPSETTING( 0x00, "On" )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
PORT_START /* IN1 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* IN2 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_COCKTAIL )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START /* DSW0 */
PORT_DIPNAME( 0x07, 0x07, "Difficulty", IP_KEY_NONE )
PORT_DIPSETTING( 0x07, "0 (Easiest)")
PORT_DIPSETTING( 0x06, "1")
PORT_DIPSETTING( 0x05, "2")
PORT_DIPSETTING( 0x04, "3")
PORT_DIPSETTING( 0x03, "4")
PORT_DIPSETTING( 0x02, "5")
PORT_DIPSETTING( 0x01, "6")
PORT_DIPSETTING( 0x00, "7 (Hardest)")
PORT_DIPNAME( 0x08, 0x08, "Lives", IP_KEY_NONE )
PORT_DIPSETTING( 0x08, "3" )
PORT_DIPSETTING( 0x00, "5")
PORT_DIPNAME( 0x30, 0x30, "Bonus Life", IP_KEY_NONE )
PORT_DIPSETTING( 0x30, "100000" )
PORT_DIPSETTING( 0x20, "100000 100000" )
PORT_DIPSETTING( 0x10, "150000 150000" )
PORT_DIPSETTING( 0x00, "200000 200000" )
PORT_DIPNAME( 0x40, 0x40, "Flip Screen", IP_KEY_NONE )
PORT_DIPSETTING( 0x40, "Off" )
PORT_DIPSETTING( 0x00, "On" )
PORT_BITX( 0x80, 0x80, IPT_DIPSWITCH_NAME | IPF_TOGGLE, "Service Mode", OSD_KEY_F2, IP_JOY_NONE, 0 )
PORT_DIPSETTING( 0x80, "Off" )
PORT_DIPSETTING( 0x00, "On" )
PORT_START /* DSW1 */
PORT_DIPNAME( 0x07, 0x07, "Coin A", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "4 Coins/1 Credit")
PORT_DIPSETTING( 0x01, "3 Coins/1 Credit")
PORT_DIPSETTING( 0x02, "2 Coins/1 Credit")
PORT_DIPSETTING( 0x03, "1 Coin/6 Credits")
PORT_DIPSETTING( 0x04, "1 Coin/4 Credits")
PORT_DIPSETTING( 0x05, "1 Coin/3 Credits")
PORT_DIPSETTING( 0x06, "1 Coin/2 Credits")
PORT_DIPSETTING( 0x07, "1 Coin/1 Credit")
PORT_DIPNAME( 0x38, 0x38, "Coin B", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "4 Coins/1 Credit")
PORT_DIPSETTING( 0x08, "3 Coins/1 Credit")
PORT_DIPSETTING( 0x10, "2 Coins/1 Credit")
PORT_DIPSETTING( 0x18, "1 Coin/6 Credits")
PORT_DIPSETTING( 0x20, "1 Coin/4 Credits")
PORT_DIPSETTING( 0x28, "1 Coin/3 Credits")
PORT_DIPSETTING( 0x30, "1 Coin/2 Credits")
PORT_DIPSETTING( 0x38, "1 Coin/1 Credit")
PORT_DIPNAME( 0x40, 0x40, "Allow Continue", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "No")
PORT_DIPSETTING( 0x40, "Yes" )
PORT_DIPNAME( 0x80, 0x80, "Demo sounds", IP_KEY_NONE )
PORT_DIPSETTING( 0x00, "Off")
PORT_DIPSETTING( 0x80, "On" )
PORT_START /* DSW1 */
PORT_BIT( 0x7f, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_VBLANK ) /* not sure, but likely */
INPUT_PORTS_END
static struct GfxLayout charlayout =
{
8,8, /* 8*8 characters */
1024, /* 1024 characters */
2, /* 2 bits per pixel */
{ 4, 0 },
{ 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3 },
{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
16*8 /* every char takes 16 consecutive bytes */
};
static struct GfxLayout spritelayout =
{
16,16, /* 16*16 sprites */
2048, /* 2048 sprites */
4, /* 4 bits per pixel */
{ 2048*64*8+4, 2048*64*8+0, 4, 0 },
{ 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3,
32*8+0, 32*8+1, 32*8+2, 32*8+3, 33*8+0, 33*8+1, 33*8+2, 33*8+3 },
{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16 },
64*8 /* every sprite takes 64 consecutive bytes */
};
static struct GfxLayout tilelayout =
{
32,32, /* 32*32 tiles */
512, /* 512 tiles */
4, /* 4 bits per pixel */
{ 512*256*8+4, 512*256*8+0, 4, 0 },
{
0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3,
32*16+0, 32*16+1, 32*16+2, 32*16+3, 32*16+8+0, 32*16+8+1, 32*16+8+2, 32*16+8+3,
64*16+0, 64*16+1, 64*16+2, 64*16+3, 64*16+8+0, 64*16+8+1, 64*16+8+2, 64*16+8+3,
96*16+0, 96*16+1, 96*16+2, 96*16+3, 96*16+8+0, 96*16+8+1, 96*16+8+2, 96*16+8+3,
},
{
0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16,
16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16,
24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16
},
256*8 /* every tile takes 256 consecutive bytes */
};
static struct GfxDecodeInfo gfxdecodeinfo[] =
{
/* start pointer colour start number of colours */
{ 1, 0x00000, &charlayout, 768, 64 }, /* colors 768-1023 */
{ 1, 0x08000, &tilelayout, 0, 32 }, /* colors 0-511 */
{ 1, 0x48000, &spritelayout, 512, 16 }, /* colors 512-767 */
{ -1 } /* end of array */
};
/* handler called by the 2203 emulator when the internal timers cause an IRQ */
static void irqhandler(void)
{
cpu_cause_interrupt(1,0xff);
}
static struct YM2203interface ym2203_interface =
{
2, /* 2 chips */
3500000, /* 3.5 MHz ? (hand tuned) */
{ YM2203_VOL(15,25), YM2203_VOL(15,25) },
{ 0 },
{ 0 },
{ 0 },
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