1942.c

这个是延伸mame的在wince平台下的游戏模拟器的代码

/***************************************************************************

1942 memory map (preliminary)

MAIN CPU:

0000-bfff ROM (8000-bfff banked)
cc00-cc7f Sprites
d000-d3ff Video RAM
d400-d7ff Color RAM
d800-dbff Background RAM (groups of 32 bytes, 16 code, 16 color/attribute)
e000-efff RAM

read:
c000      IN0
c001      IN1
c002      IN2
c003      DSW0
c004      DSW1
see the input_ports definition below for details on the input bits

write:
c800      command for the audio CPU
c802-c803 background scroll
c804      bit 7: flip screen
          bit 4: cpu B reset
		  bit 0: coin counter
c805      background palette bank selector
c806      bit 0-1 ROM bank selector 00=1-N5.BIN
                                    01=1-N6.BIN
                                    10=1-N7.BIN



SOUND CPU:

0000-3fff ROM
4000-47ff RAM
6000      command from the main CPU
8000      8910 #1 control
8001      8910 #1 write
c000      8910 #2 control
c001      8910 #2 write




The following doc was provided by Paul Leaman ([e-mail])


                                    1942

                            Hardware Description


                                Revision 0.4



INTRODUCTION
------------

This document describes the 1942 hardware. This will only be useful
to other emulator authors or for the curious.


LEGAL
-----

This document is freely distributable (with or without the emulator).
You may place it on a WEB page if you want.

You are free to use this information for whatever purpose you want providing
that:

* No profit is made
* You credit me somewhere in the documentation.
* The document is not changed




HARDWARE ARRANGEMENT
--------------------

1942 is a two board system. Board 1 contains 2 Z80A CPUs. One is used for
the sound, the other for the game.

The sound system uses 2 YM-2203 synth chips. These are compatible with the
AY-8910. Michael Cuddy has information (and source code) for these chips
on his Web page.

The second board contains the custom graphics hardware. There are three
graphics planes. The test screen refers to them as Scroll, Sprite and Tile.

The scroll and sprites are arranged in 16*16 blocks. The graphics ROMS
are not memory mapped. They are accessed directly by the hardware.

Early Capcom games seem to have similar hardware.


ROM descriptions:
=================

The generally available ROMs are as follows:

Board 1 - Code

Sound CPU:
1-C11.BIN       16K Sound ROM 0000-3fff

Main CPU:
1-N3.BIN        16K CODE ROM 0000-4000
1-N4.BIN        16K CODE ROM 4000-7fff
1-N5.BIN        16K CODE ROM 8000-bfff (paged)
1-N6.BIN         8K CODE ROM 8000-9fff (paged)
1-N7.BIN        16K CODE ROM 8000-bfff (paged)

1-F2.BIN         8K  Character ROM (Not mapped)

Board 2 - Graphics board
2-A5.BIN         8K TILE PLANE 1
2-A3.BIN         8K TILE PLANE 2
2-A1.BIN         8K TILE PLANE 3

2-A6.BIN         8K TILE PLANE 1
2-A4.BIN         8K TILE PLANE 2
2-A2.BIN         8K TILE PLANE 3

2-N1.BIN        16K OBJECT PLANE 1&2
2-L1.BIN        16K OBJECT PLANE 3&4

2-L2.BIN        16K OBJECT PLANE 1&2
2-N2.BIN        16K OBJECT PLANE 3&4


SOUND CPU MEMORY MAP
====================

0000-3fff Sound board CODE.
4000-47ff RAM data area and stack
6000      Sound input port. 0-0x1f
8000      PSG 1 Address
8001      PSG 1 Data
c000      PSG 2 Address
c001      PSG 2 Data

Runs in interrupt mode 1.

After initialization, Most of the sound code is driven by interrupt (0x38).
The code sits around waiting for the value in 0x6000 to change.

All Capcom games seem to share the same music hardware. The addresses of
the PSG chips and input vary according to the game.



MAIN CPU MEMORY MAP
===================

0000-bfff ROM Main code. Area (8000-bfff) is paged in

          Input ports
c000      Coin mech and start buttons
          0x10 Coin up
          0x08 Plater 4 start ????
          0x04 Player 3 start ????
          0x02 Player 2 start
          0x01 Player 1 start
c001      Joystick
c002      Joystick
c003      DIP switch 1 (1=off 0=on)
c004      DIP switch 2 (1=off 0=on)

          Output ports
c800      Sound output
c801      Unused
c802      Scroll register (lower 4 bits smooth, upper 4 bits rough)
c803      Scroll register MSB
c804      Watchdog circuit flip-flop ????
c805      Unknown
c806      Bits
            0-1 ROM paging   0=1-N5.BIN
                             1=1-N6.BIN
                             2=1-N7.BIN

          Video
cc00-cc7f Sprite RAM
          32 * 4 bytes

d000-d3ff Character RAM
d400-d7ff Character attribute
          Bits
             0x80 MSB character
             0x40
             0x20
             rest Attribute
d800-dbff Scroll RAM / attributes
             Alternating 16 byte rows of characters / attributes

             Attribute
                0x80 MSB tile
                0x40 Flip X
                0x20 Flip Y
                rest Attribute
e000-efff    RAM data / stack area
F000-FFFF    Unused

Game runs in interrupt mode 0 (the devices supply the interrupt number).

Two interrupts must be triggered per refresh for the game to function
correctly.

0x10 is the video retrace. This controls the speed of the game and generally
     drives the code. This must be triggerd for each video retrace.
0x08 is the sound card service interupt. The game uses this to throw sounds
     at the sound CPU.



Character RAM arrangement
-------------------------

The characters are rotated 90 degrees vertically. Each column is 32 bytes.

The attributes are arranged so that they correspond to each column.

Attribute
      0x80  Char MSB Set to get characters from 0x100 to 0x1ff
      0x40  Unknown
      rest  Character palette colour.


Tile system
-----------

Tiles are arranged in rotational buffer. Each line consists of 32 bytes.
The first 16 bytes are the tile values, the second 16 bytes contain the
attributes.

This arrangement may vary according to the machine. For example, Vulgus,
which is a horizontal/ vertical scroller uses 32 bytes per line. The
attributes are in a separate block of memory. This is probably done to
accommodate horizontal scrolling.

      0x80 Tile MSB (Set to obtain tiles 0x100-0x1ff.
      0x40 Tile flip X
      0x20 Tile Flip Y
      rest Palette colour scheme.

The scroll rough register determines the starting point for the bottom of the
screen. The buffer is circular. The bottom of the screen is at the start of
tile memory. To address the start of a line:

     lineaddress=(roughscroll * 0x20) & 0x3ff
     attributeaddress=lineaddress+0x10

Make sure to combine the MSB value to make up the rough scroll address.


Sprite arrangement
------------------

Sprites are 16*16 blocks. Attribute bits determine whether or not the
sprite is wider.

32 Sprites. 4 bytes for each sprite
    00 Sprite number 0-255
    01 Colour Code
         0x80 Sprite number MSB (256-512)
         0x40 Sprite size 16*64 (Very wide sprites)
         0x20 Sprite size 16*32 (Wide sprites)
         0x10 Sprite Y position MSB
         rest colour code
    02 Sprite X position
    03 Sprite Y position

The sprite sequence is slightly odd within the sprite data ROMS. It is
necessary to swap sprites 0x0080-0x00ff with sprites 0x0100-0x017f to get
the correct order. This is best done at load-up time.

If 0x40 is set, the next 4 sprite objects are combined into one from left
to right.
if 0x20 is set, the next 2 sprite objects are combined into one from left
to right.
if none of the above bits are set, the sprite is a simple 16*16 object.


Sprite clipping:
----------------

The title sprites are supposed to appear to move into each other. I
have not yet found the mechanism to do this.


Palette:
--------

Palette system is in hardware. There are 16 colours for each component (char,
scroll and object).

The .PAL file format used by the emulator is as follows:

Offset
0x0000-0x000f Char 16 colour palette colours
0x0010-0x001f Scroll 16 colour palette colours
0x0020-0x002f Object 16 colour palette colours
0x0030-0x00f0 Char colour schemes (3 bytes each). Values are 0-0xff
0x00f0-0x01ef Object colour scheme (16 bytes per scheme)
0x01f0-0x02ef Scroll colour scheme (8 bytes per scheme)

Note that only half the colour schemes are shown on the scroll palette
screen. The game uses colour values that are not shown. There must
be some mirroring here. Either that, or I have got the scheme wrong.



Interesting RAM locations:
--------------------------

0xE09B - Number of rolls



Graphics format:
----------------

Roberto Ventura has written a document, detailing the Ghosts 'n' Goblins
graphics layout. This can be found on the repository.


Schematics:
-----------

Schematics for Commando can be found at:

This game is fairly similar to 1942.



DIP Switch Settings
-------------------


WWW.SPIES.COM contains DIP switch settings.


***************************************************************************/

#include "driver.h"
#include "vidhrdw/generic.h"



extern unsigned char *c1942_backgroundram;
extern int c1942_backgroundram_size;
extern unsigned char *c1942_scroll;
extern unsigned char *c1942_palette_bank;
int c1942_vh_start(void);
void c1942_vh_stop(void);
void c1942_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
void c1942_background_w(int offset,int data);
void c1942_palette_bank_w(int offset,int data);
void c1942_flipscreen_w(int offset,int data);
void c1942_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);



void c1942_bankswitch_w(int offset,int data)
{
	int bankaddress;
	unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];


	bankaddress = 0x10000 + (data & 0x03) * 0x4000;
	cpu_setbank(1,&RAM[bankaddress]);
}



int c1942_interrupt(void)
{
	if (cpu_getiloops() != 0) return 0x00cf;	/* RST 08h */
	else return 0x00d7;	/* RST 10h - vblank */
}



static struct MemoryReadAddress readmem[] =
{
	{ 0x0000, 0x7fff, MRA_ROM },
	{ 0x8000, 0xbfff, MRA_BANK1 },
	{ 0xc000, 0xc000, input_port_0_r },	/* IN0 */
	{ 0xc001, 0xc001, input_port_1_r },	/* IN1 */
	{ 0xc002, 0xc002, input_port_2_r },	/* IN2 */
	{ 0xc003, 0xc003, input_port_3_r },	/* DSW0 */
	{ 0xc004, 0xc004, input_port_4_r },	/* DSW1 */
	{ 0xd000, 0xdbff, MRA_RAM },
	{ 0xe000, 0xefff, MRA_RAM },
	{ -1 }	/* end of table */
};

static struct MemoryWriteAddress writemem[] =
{
	{ 0x0000, 0xbfff, MWA_ROM },
	{ 0xc800, 0xc800, soundlatch_w },
	{ 0xc802, 0xc803, MWA_RAM, &c1942_scroll },
	{ 0xc804, 0xc804, c1942_flipscreen_w },
	{ 0xc805, 0xc805, c1942_palette_bank_w, &c1942_palette_bank },
	{ 0xc806, 0xc806, c1942_bankswitch_w },
	{ 0xcc00, 0xcc7f, MWA_RAM, &spriteram, &spriteram_size },
	{ 0xd000, 0xd3ff, videoram_w, &videoram, &videoram_size },
	{ 0xd400, 0xd7ff, colorram_w, &colorram },
	{ 0xd800, 0xdbff, c1942_background_w, &c1942_backgroundram, &c1942_backgroundram_size },
	{ 0xe000, 0xefff, MWA_RAM },
	{ -1 }	/* end of table */
};



static struct MemoryReadAddress sound_readmem[] =
{
	{ 0x0000, 0x3fff, MRA_ROM },
	{ 0x4000, 0x47ff, MRA_RAM },
	{ 0x6000, 0x6000, soundlatch_r },
	{ -1 }	/* end of table */
};

static struct MemoryWriteAddress sound_writemem[] =
{
	{ 0x0000, 0x3fff, MWA_ROM },
	{ 0x4000, 0x47ff, MWA_RAM },
	{ 0x8000, 0x8000, AY8910_control_port_0_w },
	{ 0x8001, 0x8001, AY8910_write_port_0_w },
	{ 0xc000, 0xc000, AY8910_control_port_1_w },
	{ 0xc001, 0xc001, AY8910_write_port_1_w },
	{ -1 }	/* end of table */
};