📄 cpufunc.c
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/*
CPU-function calls
CPU-Emulation based on ideas by Bernd Schmidt
Improved by Markus Gietzen
Disassembler written by Bernd Schmidt
*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include "cpudefs.h"
#include "cputbl.h"
#include "readcpu.h"
#define CPU_EMU_SIZE 0
struct cputbl {
cpuop_func *handler;
int specific;
UWORD opcode;
};
int areg_byteinc[] = {1,1,1,1,1,1,1,2};
int imm8_table[] = {8,1,2,3,4,5,6,7};
UBYTE aslmask_ubyte[] = {0x80,0xc0,0xe0,0xf0,0xf8,0xfc,0xfe,0xff};
UWORD aslmask_uword[] = {0x8000,0xc000,0xe000,0xf000,
0xf800,0xfc00,0xfe00,0xff00,
0xff80,0xffc0,0xffe0,0xfff0,
0xfff8,0xfffc,0xfffe,0xffff};
ULONG aslmask_ulong[] = {0x80000000,0xc0000000,0xe0000000,0xf0000000,
0xf8000000,0xfc000000,0xfe000000,0xff000000,
0xff800000,0xffc00000,0xffe00000,0xfff00000,
0xfff80000,0xfffc0000,0xfffe0000,0xffff0000,
0xffff8000,0xffffc000,0xffffe000,0xfffff000,
0xfffff800,0xfffffc00,0xfffffe00,0xffffff00,
0xffffff80,0xffffffc0,0xffffffe0,0xfffffff0,
0xfffffff8,0xfffffffc,0xfffffffe,0xffffffff};
struct instr_def defs68k[] = {
{ 60, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "ORSR.B #1"},
{ 124, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "ORSR.W #1"},
{ 0, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "OR.z #z,d[!Areg]"},
{ 572, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "ANDSR.B #1"},
{ 636, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "ANDSR.W #1"},
{ 512, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "AND.z #z,d[!Areg]"},
{ 1024, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "SUB.z #z,d[!Areg]"},
{ 1536, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "ADD.z #z,d[!Areg]"},
{ 2048, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "BTST #1,s[!Areg]"},
{ 2112, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "BCHG #1,s[!Areg,Immd]"},
{ 2176, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "BCLR #1,s[!Areg,Immd]"},
{ 2240, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "BSET #1,s[!Areg,Immd]"},
{ 2620, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "EORSR.B #1"},
{ 2684, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "EORSR.W #1"},
{ 2560, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "EOR.z #z,d[!Areg]"},
{ 3072, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 65280, 0, "CMP.z #z,s[!Areg,Immd]"},
{ 256, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "MVPMR.W d[Areg-Ad16],Dr"},
{ 320, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "MVPMR.L d[Areg-Ad16],Dr"},
{ 384, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "MVPRM.W Dr,d[Areg-Ad16]"},
{ 448, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "MVPRM.L Dr,d[Areg-Ad16]"},
{ 256, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "BTST Dr,s[!Areg]"},
{ 320, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "BCHG Dr,s[!Areg,Immd]"},
{ 384, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "BCLR Dr,s[!Areg,Immd]"},
{ 448, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "BSET Dr,s[!Areg,Immd]"},
{ 4096, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, "MOVE.B s,d[!Areg]"},
{ 8192, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, "MOVEA.L s,d[Areg]"},
{ 8192, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, "MOVE.L s,d[!Areg]"},
{ 12288, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, "MOVEA.W s,d[Areg]"},
{ 12288, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, "MOVE.W s,d[!Areg]"},
{ 16384, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "NEGX.z d[!Areg]"},
{ 16576, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 1, "MVSR2.W d[!Areg]"},
{ 16896, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "CLR.z d[!Areg]"},
{ 17408, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "NEG.z d[!Areg]"},
{ 17600, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "MV2SR.B s[!Areg]"},
{ 17920, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, "NOT.z d[!Areg]"},
{ 18112, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, "MV2SR.W s[!Areg]"},
{ 18432, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "NBCD.B d[!Areg]"},
{ 18496, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "SWAP.W s[Dreg]"},
{ 18496, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
{ 18560, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "EXT.W d[Dreg]"},
{ 18560, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "MVMLE.W #1,d[!Dreg,Areg,Aipi]"},
{ 18624, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "EXT.L d[Dreg]"},
{ 18624, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "MVMLE.L #1,d[!Dreg,Areg,Aipi]"},
{ 18880, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "EXT.B d[Dreg]"},
{ 18944, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 65280, 0, "TST.z s"},
{ 19136, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "TAS.B d[!Areg]"},
{ 19196, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "ILLEGAL"},
{ 19584, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]"},
{ 19648, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]"},
{ 20032, 4, {8,8,8,8,0,0,0,0,0,0,0,0,0,0,0,0}, 65520, 0, "TRAP #J"},
{ 20048, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, "LINK.W Ar,#1"},
{ 20056, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, "UNLK.L Ar"},
{ 20064, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 2, "MVR2USP.L Ar"},
{ 20072, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 2, "MVUSP2R.L Ar"},
{ 20080, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "RESET"},
{ 20081, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "NOP"},
{ 20082, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "STOP #1"},
{ 20083, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, "RTE"},
{ 20084, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "RTD #1"},
{ 20085, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "RTS"},
{ 20086, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "TRAPV"},
{ 20087, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "RTR"},
{ 20096, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
{ 16640, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "CHK.L s[!Areg],Dr"},
{ 16768, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "CHK.W s[!Areg],Dr"},
{ 20160, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, "JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
{ 16832, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar"},
{ 20480, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "ADDA.z #j,d[Areg]"},
{ 20480, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "ADD.z #j,d[!Areg]"},
{ 20736, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "SUBA.z #j,d[Areg]"},
{ 20736, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "SUB.z #j,d[!Areg]"},
{ 20680, 7, {2,2,2,2,15,15,15,0,0,0,0,0,0,0,0,0}, 61688, 0, "DBcc.W Dr,#1"},
{ 20672, 10, {2,2,2,2,13,13,13,14,14,14,0,0,0,0,0,0}, 61632, 0, "Scc.B d[!Areg]"},
{ 24832, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "BSR.W #1"},
{ 24832, 8, {6,6,6,6,6,6,6,6,0,0,0,0,0,0,0,0}, 65280, 0, "BSR.B #i"},
{ 25087, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, "BSR.L #2"},
{ 24576, 4, {3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 0, "Bcc.W #1"},
{ 24576, 12, {3,3,3,3,6,6,6,6,6,6,6,6,0,0,0,0}, 61440, 0, "Bcc.B #i"},
{ 24831, 4, {3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 0, "Bcc.L #2"},
{ 28672, 11, {15,15,15,5,5,5,5,5,5,5,5,0,0,0,0,0}, 61696, 0, "MOVE.L #i,Dr"},
{ 32768, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, "OR.z s[!Areg],Dr"},
{ 32960, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "DIVU.W s[!Areg],Dr"},
{ 33024, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "SBCD.B d[Dreg],Dr"},
{ 33024, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "SBCD.B d[Areg-Apdi],Arp"},
{ 33024, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "OR.z Dr,d[!Areg,Dreg]"},
{ 33216, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "DIVS.W s[!Areg],Dr"},
{ 36864, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, "SUB.z s,Dr"},
{ 37056, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "SUBA.W s,Ar"},
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "SUBX.z d[Dreg],Dr"},
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "SUBX.z d[Areg-Apdi],Arp"},
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "SUB.z Dr,d[!Areg,Dreg]"},
{ 37312, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "SUBA.L s,Ar"},
{ 45056, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, "CMP.z s,Dr"},
{ 45248, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "CMPA.W s,Ar"},
{ 45504, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "CMPA.L s,Ar"},
{ 45312, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "CMPM.z d[Areg-Aipi],ArP"},
{ 45312, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "EOR.z Dr,d[!Areg]"},
{ 49152, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, "AND.z s[!Areg],Dr"},
{ 49344, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "MULU.W s[!Areg],Dr"},
{ 49408, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "ABCD.B d[Dreg],Dr"},
{ 49408, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "ABCD.B d[Areg-Apdi],Arp"},
{ 49408, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "AND.z Dr,d[!Areg,Dreg]"},
{ 49472, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "EXG.L Dr,d[Dreg]"},
{ 49472, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "EXG.L Ar,d[Areg]"},
{ 49536, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, "EXG.L Dr,d[Areg]"},
{ 49600, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "MULS.W s[!Areg],Dr"},
{ 53248, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, "ADD.z s,Dr"},
{ 53440, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "ADDA.W s,Ar"},
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "ADDX.z d[Dreg],Dr"},
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "ADDX.z d[Areg-Apdi],Arp"},
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, "ADD.z Dr,d[!Areg,Dreg]"},
{ 53696, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, "ADDA.L s,Ar"},
{ 57344, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ASf.z #j,DR"},
{ 57352, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "LSf.z #j,DR"},
{ 57360, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ROXf.z #j,DR"},
{ 57368, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ROf.z #j,DR"},
{ 57376, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ASf.z Dr,DR"},
{ 57384, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "LSf.z Dr,DR"},
{ 57392, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ROXf.z Dr,DR"},
{ 57400, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, "ROf.z Dr,DR"},
{ 57536, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, "ASfW.W d[!Dreg,Areg]"},
{ 58048, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, "LSfW.W d[!Dreg,Areg]"},
{ 58560, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, "ROXfW.W d[!Dreg,Areg]"},
{ 59072, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, "ROfW.W d[!Dreg,Areg]"}};
int n_defs68k=124;
struct cputbl smallcputbl[] = {
{ op_0, 0, 0 }, /* OR */
{ op_10, 0, 16 }, /* OR */
{ op_18, 0, 24 }, /* OR */
{ op_20, 0, 32 }, /* OR */
{ op_28, 0, 40 }, /* OR */
{ op_30, 0, 48 }, /* OR */
{ op_38, 0, 56 }, /* OR */
{ op_39, 0, 57 }, /* OR */
{ op_3c, 0, 60 }, /* ORSR */
{ op_40, 0, 64 }, /* OR */
{ op_50, 0, 80 }, /* OR */
{ op_58, 0, 88 }, /* OR */
{ op_60, 0, 96 }, /* OR */
{ op_68, 0, 104 }, /* OR */
{ op_70, 0, 112 }, /* OR */
{ op_78, 0, 120 }, /* OR */
{ op_79, 0, 121 }, /* OR */
{ op_7c, 0, 124 }, /* ORSR */
{ op_80, 0, 128 }, /* OR */
{ op_90, 0, 144 }, /* OR */
{ op_98, 0, 152 }, /* OR */
{ op_a0, 0, 160 }, /* OR */
{ op_a8, 0, 168 }, /* OR */
{ op_b0, 0, 176 }, /* OR */
{ op_b8, 0, 184 }, /* OR */
{ op_b9, 0, 185 }, /* OR */
{ op_100, 0, 256 }, /* BTST */
{ op_108, 0, 264 }, /* MVPMR */
{ op_110, 0, 272 }, /* BTST */
{ op_118, 0, 280 }, /* BTST */
{ op_120, 0, 288 }, /* BTST */
{ op_128, 0, 296 }, /* BTST */
{ op_130, 0, 304 }, /* BTST */
{ op_138, 0, 312 }, /* BTST */
{ op_139, 0, 313 }, /* BTST */
{ op_13a, 0, 314 }, /* BTST */
{ op_13b, 0, 315 }, /* BTST */
{ op_13c, 0, 316 }, /* BTST */
{ op_140, 0, 320 }, /* BCHG */
{ op_148, 0, 328 }, /* MVPMR */
{ op_150, 0, 336 }, /* BCHG */
{ op_158, 0, 344 }, /* BCHG */
{ op_160, 0, 352 }, /* BCHG */
{ op_168, 0, 360 }, /* BCHG */
{ op_170, 0, 368 }, /* BCHG */
{ op_178, 0, 376 }, /* BCHG */
{ op_179, 0, 377 }, /* BCHG */
{ op_17a, 0, 378 }, /* BCHG */
{ op_17b, 0, 379 }, /* BCHG */
{ op_180, 0, 384 }, /* BCLR */
{ op_188, 0, 392 }, /* MVPRM */
{ op_190, 0, 400 }, /* BCLR */
{ op_198, 0, 408 }, /* BCLR */
{ op_1a0, 0, 416 }, /* BCLR */
{ op_1a8, 0, 424 }, /* BCLR */
{ op_1b0, 0, 432 }, /* BCLR */
{ op_1b8, 0, 440 }, /* BCLR */
{ op_1b9, 0, 441 }, /* BCLR */
{ op_1ba, 0, 442 }, /* BCLR */
{ op_1bb, 0, 443 }, /* BCLR */
{ op_1c0, 0, 448 }, /* BSET */
{ op_1c8, 0, 456 }, /* MVPRM */
{ op_1d0, 0, 464 }, /* BSET */
{ op_1d8, 0, 472 }, /* BSET */
{ op_1e0, 0, 480 }, /* BSET */
{ op_1e8, 0, 488 }, /* BSET */
{ op_1f0, 0, 496 }, /* BSET */
{ op_1f8, 0, 504 }, /* BSET */
{ op_1f9, 0, 505 }, /* BSET */
{ op_1fa, 0, 506 }, /* BSET */
{ op_1fb, 0, 507 }, /* BSET */
{ op_200, 0, 512 }, /* AND */
{ op_210, 0, 528 }, /* AND */
{ op_218, 0, 536 }, /* AND */
{ op_220, 0, 544 }, /* AND */
{ op_228, 0, 552 }, /* AND */
{ op_230, 0, 560 }, /* AND */
{ op_238, 0, 568 }, /* AND */
{ op_239, 0, 569 }, /* AND */
{ op_23c, 0, 572 }, /* ANDSR */
{ op_240, 0, 576 }, /* AND */
{ op_250, 0, 592 }, /* AND */
{ op_258, 0, 600 }, /* AND */
{ op_260, 0, 608 }, /* AND */
{ op_268, 0, 616 }, /* AND */
{ op_270, 0, 624 }, /* AND */
{ op_278, 0, 632 }, /* AND */
{ op_279, 0, 633 }, /* AND */
{ op_27c, 0, 636 }, /* ANDSR */
{ op_280, 0, 640 }, /* AND */
{ op_290, 0, 656 }, /* AND */
{ op_298, 0, 664 }, /* AND */
{ op_2a0, 0, 672 }, /* AND */
{ op_2a8, 0, 680 }, /* AND */
{ op_2b0, 0, 688 }, /* AND */
{ op_2b8, 0, 696 }, /* AND */
{ op_2b9, 0, 697 }, /* AND */
{ op_400, 0, 1024 }, /* SUB */
{ op_410, 0, 1040 }, /* SUB */
{ op_418, 0, 1048 }, /* SUB */
{ op_420, 0, 1056 }, /* SUB */
{ op_428, 0, 1064 }, /* SUB */
{ op_430, 0, 1072 }, /* SUB */
{ op_438, 0, 1080 }, /* SUB */
{ op_439, 0, 1081 }, /* SUB */
{ op_440, 0, 1088 }, /* SUB */
{ op_450, 0, 1104 }, /* SUB */
{ op_458, 0, 1112 }, /* SUB */
{ op_460, 0, 1120 }, /* SUB */
{ op_468, 0, 1128 }, /* SUB */
{ op_470, 0, 1136 }, /* SUB */
{ op_478, 0, 1144 }, /* SUB */
{ op_479, 0, 1145 }, /* SUB */
{ op_480, 0, 1152 }, /* SUB */
{ op_490, 0, 1168 }, /* SUB */
{ op_498, 0, 1176 }, /* SUB */
{ op_4a0, 0, 1184 }, /* SUB */
{ op_4a8, 0, 1192 }, /* SUB */
{ op_4b0, 0, 1200 }, /* SUB */
{ op_4b8, 0, 1208 }, /* SUB */
{ op_4b9, 0, 1209 }, /* SUB */
{ op_600, 0, 1536 }, /* ADD */
{ op_610, 0, 1552 }, /* ADD */
{ op_618, 0, 1560 }, /* ADD */
{ op_620, 0, 1568 }, /* ADD */
{ op_628, 0, 1576 }, /* ADD */
{ op_630, 0, 1584 }, /* ADD */
{ op_638, 0, 1592 }, /* ADD */
{ op_639, 0, 1593 }, /* ADD */
{ op_640, 0, 1600 }, /* ADD */
{ op_650, 0, 1616 }, /* ADD */
{ op_658, 0, 1624 }, /* ADD */
{ op_660, 0, 1632 }, /* ADD */
{ op_668, 0, 1640 }, /* ADD */
{ op_670, 0, 1648 }, /* ADD */
{ op_678, 0, 1656 }, /* ADD */
{ op_679, 0, 1657 }, /* ADD */
{ op_680, 0, 1664 }, /* ADD */
{ op_690, 0, 1680 }, /* ADD */
{ op_698, 0, 1688 }, /* ADD */
{ op_6a0, 0, 1696 }, /* ADD */
{ op_6a8, 0, 1704 }, /* ADD */
{ op_6b0, 0, 1712 }, /* ADD */
{ op_6b8, 0, 1720 }, /* ADD */
{ op_6b9, 0, 1721 }, /* ADD */
{ op_800, 0, 2048 }, /* BTST */
{ op_810, 0, 2064 }, /* BTST */
{ op_818, 0, 2072 }, /* BTST */
{ op_820, 0, 2080 }, /* BTST */
{ op_828, 0, 2088 }, /* BTST */
{ op_830, 0, 2096 }, /* BTST */
{ op_838, 0, 2104 }, /* BTST */
{ op_839, 0, 2105 }, /* BTST */
{ op_83a, 0, 2106 }, /* BTST */
{ op_83b, 0, 2107 }, /* BTST */
{ op_83c, 0, 2108 }, /* BTST */
{ op_840, 0, 2112 }, /* BCHG */
{ op_850, 0, 2128 }, /* BCHG */
{ op_858, 0, 2136 }, /* BCHG */
{ op_860, 0, 2144 }, /* BCHG */
{ op_868, 0, 2152 }, /* BCHG */
{ op_870, 0, 2160 }, /* BCHG */
{ op_878, 0, 2168 }, /* BCHG */
{ op_879, 0, 2169 }, /* BCHG */
{ op_87a, 0, 2170 }, /* BCHG */
{ op_87b, 0, 2171 }, /* BCHG */
{ op_880, 0, 2176 }, /* BCLR */
{ op_890, 0, 2192 }, /* BCLR */
{ op_898, 0, 2200 }, /* BCLR */
{ op_8a0, 0, 2208 }, /* BCLR */
{ op_8a8, 0, 2216 }, /* BCLR */
{ op_8b0, 0, 2224 }, /* BCLR */
{ op_8b8, 0, 2232 }, /* BCLR */
{ op_8b9, 0, 2233 }, /* BCLR */
{ op_8ba, 0, 2234 }, /* BCLR */
{ op_8bb, 0, 2235 }, /* BCLR */
{ op_8c0, 0, 2240 }, /* BSET */
{ op_8d0, 0, 2256 }, /* BSET */
{ op_8d8, 0, 2264 }, /* BSET */
{ op_8e0, 0, 2272 }, /* BSET */
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