📄 efd_conf.h
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/* ###########################################################################
### Intel Confidential
### Copyright (c) Intel Corporation 2007
### All Rights Reserved.
### ----------------------------------------------------------------------
### Project: Intel Flash Driver
###
### Module: efd_conf.h
###
### $Archive: $
### $Revision: $
### $Date: $
###
### $NoKeywords: $
##############################################################################
###
### NOTICE OF LICENSE AGREEMENT
###
### This code is provided by Intel Corp., and the use is governed
### under the terms of a license agreement. See license agreement
### for complete terms of license.
###
### YOU MAY ONLY USE THE SOFTWARE SUBJECT TO THE TERMS OF THE
### INTEL SOFTWARE LICENSE AGREEMENT.
###
########################################################################### */
#ifndef _EFD_CONF_H_
#define _EFD_CONF_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
It is configuration file for:
- A33 Intel PCM Memory
- x16 (16bit bus width flash chip connected)
- Nucleus
*/
/*
Configuration list for customer purposes. There is possibility
to enable/disable individual operations to reduce code size.
*/
#define EFD_CONF_DEVICE_ID TRUE
#define EFD_CONF_CFI TRUE
#define EFD_CONF_CFI_EX TRUE
#define EFD_CONF_BUFFERED_WRITE TRUE
#define EFD_CONF_SUSPEND TRUE
#define EFD_CONF_RESUME TRUE
#define EFD_CONF_BLOCK_SUSPEND TRUE
#define EFD_CONF_BLOCK_RESUME TRUE
#define EFD_CONF_BLOCK_STATE TRUE
#define EFD_CONF_BLOCK_LOCKDOWN TRUE
#define EFD_CONF_READ_STATUS TRUE
#define EFD_CONF_CLEAR_STATUS TRUE
#define EFD_CONF_READ_PR TRUE
#define EFD_CONF_WRITE_PR TRUE
#define EFD_CONF_BA_WRITE TRUE
#define EFD_CONF_BA_BUFFERED_WRITE TRUE
#define EFD_CONF_STREAM_MODE TRUE
/*
* Describe to the flash chip configuration for the hardware
*/
#define FLASH_TYPE_A33
/*****************************************************************************
*
* BASE_ADDR
*
* DESCRIPTION:
* Base Address
*
* The start address where the flash memory chips are "visible" within
* the memory of the CPU is called the BASE_ADDR. This address must be
* set according to the current system.
*
* USAGE:
*
*****************************************************************************/
#ifndef BASE_ADDR
#define BASE_ADDR 0xE0000000
#endif /* BASE_ADDR */
/*****************************************************************************
*
* USED_CONFIGURATION
*
* DESCRIPTION:
* Flash and Board Configuration
*
* The driver supports also different configurations of the flash chips
* on the board. In each configuration a new data Type called
* 'FLASHDATA' is defined to match the current CPU data bus width.
* This data type is then used for all accesses to the memory.
*
* The different options (defines) are explained below:
*
* USAGE:
*
*****************************************************************************/
#define _8BIT_1_X8_ 1 /* no-interleaving, a single x8 device */
#define _16BIT_1_X16_ 2 /* no-interleaving, a single x16 device in x16 mode */
#define _16BIT_2_X8_ 3 /* two x8 devices interleaved to form x16 */
#define _32BIT_1_X32_ 4 /* no-interleaving, a single x32 device in x32 mode */
#define _32BIT_2_X16_ 5 /* two x16 devices interleaved to form x32 */
#define _32BIT_4_X8_ 6 /* four x8 devices interleaved to form x32 */
#ifndef USED_CONFIGURATION
#define USED_CONFIGURATION _16BIT_1_X16_
#endif /* USED_CONFIGURATION */
/*****************************************************************************
*
* DBG_LEVEL
*
* DESCRIPTION:
* Currently the Error String Definition
*
The drivers provides also a subroutine which displays the full
error message instead of just an error number.
*
* USAGE:
*
*****************************************************************************/
#define SILENT 1
#define VERBOSE 2
#ifndef DBG_LEVEL
#define DBG_LEVEL VERBOSE
#endif /* DBG_LEVEL */
#ifdef __cplusplus
}
#endif
#endif /* _EFD_CONF_H_ */
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