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📄 device.h

📁 intel p33 driver file
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/*************************************************************************
 *** Intel Confidential
 *** Copyright (C) Intel Corporation 2003-2005
 *** All Rights Reserved.
 *** --------------------------------------------------------------------
 ***
 *** Project Name: Flash Templates
 ***
 *** Module Name: Device
 ***
 *** File: Device.H - P33 device specific template C header
 ***
 *** File Revision: $Revision: 2 $, $JustDate:  10/11/06 $, $Author: smangrul $
 ***
 *** Purpose:
 ***
 ***    The purpose of this file is to establish P33 device specific
 ***    constants used at compile time and runtime.  These constants
 ***    include device layout parameters, command constants and
 ***    function declaration flags.
 ***
 *** $NoKeywords: $
 *************************************************************************/

/*
*****************************************************************
* NOTICE OF LICENSE AGREEMENT
*
* This code is provided by Intel Corp., and the use is governed
* under the terms of a license agreement. See license agreement
* for complete terms of license.
*
* YOU MAY ONLY USE THE SOFTWARE WITH INTEL FLASH PRODUCTS.  YOUR
* USE OF THE SOFTWARE WITH ANY OTHER FLASH PRODUCTS IS EXPRESSLY
* PROHIBITED UNLESS AND UNTIL YOU APPLY FOR, AND ARE GRANTED IN
* INTEL'S SOLE DISCRETION, A SEPARATE WRITTEN SOFTWARE LICENSE
* FROM INTEL LICENSING ANY SUCH USE.
*****************************************************************
*/

#ifndef __DEVICE_H  /* ensure this file only gets included once */
    #define __DEVICE_H

/*
 * P33 specific constants
 */

/* compile flags:  set 1 flag for each and every template
 * function.  These are used at compile time to identify
 * implementation location (common.c or device.c specific)
 * of each function.
*/

/* set compile flags to identify functions which ARE
    implemented as device specific (i.e. will use these
    device.c functions for this template ).  Setting these
    constants to TRUE indicates that common template.c
    implementations of these functions will NOT be
    used. */

    #define DEVICE_ERASE_ALL_BLOCKS         TRUE
    #define DEVICE_ERASE_SUSPEND            TRUE
    #define DEVICE_EXTENDED_QUERY           TRUE
    #define DEVICE_GET_BLOCK_ADDRESS        TRUE
    #define DEVICE_LOCK_BLOCK               TRUE
    #define DEVICE_LOCK_PROTECTION          TRUE
    #define DEVICE_PAGE_MODE                TRUE
    #define DEVICE_PROGRAM_FLASH_BUFFERED   TRUE
    #define DEVICE_PROGRAM_PROTECTION       TRUE
    #define DEVICE_PROGRAM_SUSPEND          TRUE
    #define DEVICE_READ_BLOCK_STATUS        TRUE
    #define DEVICE_READF                    FALSE       /* Turned off for extender card function */
    #define DEVICE_READ_PROTECTION          TRUE
    #define DEVICE_RESUME                   TRUE
    #define DEVICE_UNLOCK_ALL_BLOCKS        TRUE
    #define DEVICE_WRITEF                   FALSE       /* Turned off for extender card function */

/* set compile flags to identify functions which are NOT
    implemented as device specific (i.e. will use the
    common.c functions for these functions */


    #define DEVICE_CLEAR_STATUS             FALSE
    #define DEVICE_ERASE_BLOCK              FALSE
    #define DEVICE_GET_QUERY_ADDRESS        FALSE
    #define DEVICE_LOCK_DOWN_BLOCK          FALSE
    #define DEVICE_PROGRAM_FLASH            FALSE
    #define DEVICE_QUERY                    FALSE
    #define DEVICE_READ_DEVICE_ID           FALSE
    #define DEVICE_READ_FLASH               FALSE
    #define DEVICE_READ_STATUS              FALSE
    #define DEVICE_SEC_EXTENDED_QUERY       FALSE
    #define DEVICE_UNLOCK_BLOCK             FALSE
    #define DEVICE_WAIT_UNTIL_READY         FALSE

/* TRUE means client will implement this function external to the template */
    #define CLIENT_GET_FPTR                 FALSE

/* little endian */
    #define BIG_ENDIAN_ARCHITECTURE         FALSE

/* P33 does not support X8 or paired x8 or X16 modes so these MUST always be false */
    #define X_8                             FALSE
    #define PX_16                           FALSE

/* set 1 and Only 1 configuration to TRUE */
    #define X_16                            TRUE
    #define X_32                            FALSE
    #define ILX_32                          FALSE


/* set 1 and only 1 size to TRUE */
    #define P33_64_M                        FALSE
	#define P33_128_M                       FALSE
    #define P33_256_M                       TRUE


/* set 1 and only 1 PARAMETER to TRUE */
    #define P33_TOP                         FALSE
    #define P33_BOTTOM                      TRUE


/* ERASE_TIMEOUT_CYCLES = # of times to check for status ready after erase
  commands are issued to the device */
    #define TMPL_ERASE_TIMEOUT              50000000L

/* PROGRAM_TIMEOUT_CYCLES = # of times to check for status ready after
     program commands are issued to the device */
    #define TMPL_PROGRAM_TIMEOUT            1000000L

    #define TMPL_BLOCKSTAT_UNLOCKED         0x0
    #define TMPL_BLOCKSTAT_LOCKED           0x1
    #define TMPL_BLOCKSTAT_LOCKEDDOWN       0x3

    #define TMPL_PROTECTION_LOCK_LOCATION   0x0

/* The device is divided into multiple 8-Mbit partitions. Each device contains
    one parameter partion and several main partitions.

    In top or bottom parameter partition, it contains four 16-KWord blocks
    and the rest are 64-KWord blocks.  Main partitions contain  blocks that
    are 64-Kword in size */


/******************** 64M ********************/
    #if P33_64_M
        #define TMPL_TOTAL_NUMBLOCKS        0x42

        #define TMPL_MAIN_BLOCK_NUMBYTES    0x20000         /* 64 K-Word block size */
        #define TMPL_PARM_BLOCK_NUMBYTES    0x8000          /* 16 K-Word block size */

        #define TMPL_TOP_PARTITION_BASE     0x3F0000        /* address */
        #define TMPL_BOTTOM_PARTITION_BASE  0x0000          /* address */

        #define TMPL_TOP_BLOCK_LOWER        0x3F
        #define TMPL_TOP_BLOCK_UPPER        0x42

        #define TMPL_BOTTOM_BLOCK_LOWER     0x0
        #define TMPL_BOTTOM_BLOCK_UPPER     0x3


        #define TMPL_TOTAL_SIZE             0x800000
        #define TMPL_BLOCK_MASK             0xFFFF
    #endif /* P33_64_M */

/******************** 128M ********************/
    #if P33_128_M
        #define TMPL_TOTAL_NUMBLOCKS        0x83

        #define TMPL_MAIN_BLOCK_NUMBYTES    0x20000         /* 64 K-Word block size */
        #define TMPL_PARM_BLOCK_NUMBYTES    0x8000          /* 16 K-Word block size */

        #define TMPL_TOP_PARTITION_BASE     0x7F0000        /* address */
        #define TMPL_BOTTOM_PARTITION_BASE  0x0000          /* address */

        #define TMPL_TOP_BLOCK_LOWER        0x7F
        #define TMPL_TOP_BLOCK_UPPER        0x82

        #define TMPL_BOTTOM_BLOCK_LOWER     0x0
        #define TMPL_BOTTOM_BLOCK_UPPER     0x3

        #define TMPL_TOTAL_SIZE             0x1000000
        #define TMPL_BLOCK_MASK             0xFFFF
    #endif /* P33_128_M */

/******************** 256M *******************/
    #if P33_256_M
		#define TMPL_TOTAL_NUMBLOCKS        0x103
	    #define TMPL_MAIN_BLOCK_NUMBYTES    0x20000         /* 64 K-Word block size */
        #define TMPL_PARM_BLOCK_NUMBYTES    0x8000          /* 16 K-Word block size */

		#define TMPL_BOTTOM_PARTITION_BASE  0x0000          /* address */

		/* For bottom partition device */
		#if P33_BOTTOM
			#define TMPL_TOP_PARTITION_BASE     0x20000        /* address */

			#define TMPL_TOP_BLOCK_LOWER        0x4
        	#define TMPL_TOP_BLOCK_UPPER        0x102

        	#define TMPL_BOTTOM_BLOCK_LOWER     0x0
        	#define TMPL_BOTTOM_BLOCK_UPPER     0x3
		#endif

		#if P33_TOP
			#define TMPL_TOP_PARTITION_BASE     0x1FE0000        /* address */

			#define TMPL_TOP_BLOCK_LOWER        0xFF
        	#define TMPL_TOP_BLOCK_UPPER        0x102

        	#define TMPL_BOTTOM_BLOCK_LOWER     0x0
        	#define TMPL_BOTTOM_BLOCK_UPPER     0xFE
		#endif


        #define TMPL_TOTAL_SIZE            0x2000000
        #define TMPL_BLOCK_MASK            0xFFFF


		/* This address is to calculate the Protection Register Address and the Lock Protection Address.
		 * If the device is bottom boot then any of the following four addresses would be valid :
		 * 1) TMPL_BOTTOM_PARTITION_BASE ( assuming flash base address is 0x0000 )
		 * 2) 0x20000 or TMPL_TOP_PARTITION_BASE ( block 4 )
		 * 3) 0x40000 ( block 5 )
		 * 4) 0x60000 ( block 6 )
		 *
		 * If the device is top boot then any of the following four addresses would be valid :
		 * ( assuming flash base address is 0x0000 )
		 * 1) TMPL_TOP_PARTITION_BASE
		 * 2) base address for block 254
		 * 3) base address for block 253
		 * 4) base address for block 252
		 * REFER TO SECTION 13.2.1 IN THE DATASHEET */

		#if P33_BOTTOM
			#define TMPL_OTP_BLOCK_OFFSET TMPL_BOTTOM_PARTITION_BASE
		#endif

		#if P33_TOP
			#define TMPL_OTP_BLOCK_OFFSET TMPL_TOP_PARTITION_BASE
		#endif

    #endif /* P33_256_M */



    #if X_16
		#define TMPL_OTP_NUMWORDS          0x88
        #define TMPL_OTP_BASE              0x100           /* address for lock register 0 */
        #define TMPL_OTP_BASE2             0x112           /* address for lock register 1 */
        #define TMPL_OTP_PROGRAM           0x00C0
        #define TMPL_OTP_READ              0x0090
		#define TMPL_OTP_LOCK              0xFFFD

/*  OTP Extended PR[1-16] bit settings */
        #define TMPL_OTP_LOCK_PR1           0xFFFE
        #define TMPL_OTP_LOCK_PR2           0xFFFD
        #define TMPL_OTP_LOCK_PR3           0xFFFB
        #define TMPL_OTP_LOCK_PR4           0xFFF7
        #define TMPL_OTP_LOCK_PR5           0xFFEF
        #define TMPL_OTP_LOCK_PR6           0xFFDF
        #define TMPL_OTP_LOCK_PR7           0xFFBF
        #define TMPL_OTP_LOCK_PR8           0xFF7F
        #define TMPL_OTP_LOCK_PR9           0xFEFF
        #define TMPL_OTP_LOCK_PR10          0xFDFF
        #define TMPL_OTP_LOCK_PR11          0xFBFF
        #define TMPL_OTP_LOCK_PR12          0xF7FF
        #define TMPL_OTP_LOCK_PR13          0xEFFF
        #define TMPL_OTP_LOCK_PR14          0xDFFF
        #define TMPL_OTP_LOCK_PR15          0xBFFF
        #define TMPL_OTP_LOCK_PR16          0x7FFF

        #define TMPL_LOCKDOWN_BIT_SET       0x002F
        #define TMPL_LOCK_BIT_SET           0x0001          /* 1st cycle lock bit command */
        #define TMPL_LOCK_BIT_CLEAR         0x00D0          /* 2nd cycle lock bit command */
        #define TMPL_BLOCK_SUSPEND          0x00B0
        #define TMPL_BLOCK_RESUME           0x00D0
    #endif

    #if X_32
        #define TMPL_OTP_NUMWORDS           0x90
        #define TMPL_OTP_BASE               0x200           /* address */
        #define TMPL_OTP_BASE2              0x224           /* address */
        #define TMPL_OTP_PROGRAM            0x00C000C0
        #define TMPL_OTP_READ               0x00900090
        #define TMPL_OTP_LOCK               0xFFFDFFFD
        #define TMPL_LOCKDOWN_BIT_SET       0x002D002F
        #define TMPL_LOCK_BIT_SET           0x00010001      /* 2nd cycle lock bit command */
        #define TMPL_LOCK_BIT_CLEAR         0x00D000D0      /* 2nd cycle lock bit command */
        #define TMPL_BLOCK_SUSPEND          0x00B000B0
        #define TMPL_BLOCK_RESUME           0x00D000D0
    #endif

    #if ILX_32
        #define TMPL_OTP_NUMWORDS           0x89
        #define TMPL_OTP_BASE               0x224           /* address */
        #define TMPL_OTP_BASE2              0x224           /* address */
        #define TMPL_OTP_PROGRAM            0x00C000C0
        #define TMPL_OTP_READ               0x00900090
        #define TMPL_OTP_LOCK               0xFFFDFFFD
        #define TMPL_LOCKDOWN_BIT_SET       0x002F002F
        #define TMPL_LOCK_BIT_SET           0x00010001      /* 2nd cycle lock bit command */
        #define TMPL_LOCK_BIT_CLEAR         0x00D000D0      /* 2nd cycle lock bit command */
        #define TMPL_BLOCK_SUSPEND          0x00B000B0
        #define TMPL_BLOCK_RESUME           0x00D000D0
    #endif


/********************************************************************
    PRODUCT SPECIFIC DATA DEFINES
********************************************************************/

    #if X_16
        #define TMPL_BUFFER_SIZE            0x20            /* words */
        #define TMPL_WRITE_TO_BUFFER        0x00E8
        #define TMPL_SET_READ_CONFIG        0x0003
    #endif

    #if X_32
        #define TMPL_BUFFER_SIZE            0x40            /* words */
        #define TMPL_WRITE_TO_BUFFER        0x00E800E8
        #define TMPL_SET_READ_CONFIG        0x00030003
    #endif

    #if ILX_32
        #define TMPL_BUFFER_SIZE            0x40            /* words */
        #define TMPL_WRITE_TO_BUFFER        0x00E800E8
        #define TMPL_SET_READ_CONFIG        0x00030003
    #endif


	/* defined for all data widths. contains A16..A1 */
	#define TMPL_STD_READ_MODE              0x3FCF
    #define TMPL_PAGE_READ_MODE             0xBFCF


/*
 * device specific typedefs
 */

/* extended query structure */
typedef struct TMPL_ExtQueryData
{
    char   ExtQueryStr[4];        /* 3 bytes + null */
    UINT8  MajorVersionNum;       /* 1 byte */
    UINT8  MinorVersionNum;       /* 1 bytes */
    UINT32 OptionalFeature;       /* 4 bytes */
    UINT8  AfterSuspendFunctions; /* 1 byte */
    UINT16 BlockLockStatus;       /* 2 bytes */
    UINT8  VccOptimum;            /* 1 byte */
    UINT8  VppOptimum;            /* 1 byte */
} TMPL_extquery;



#endif  /* __DEVICE_H */

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