decoder.do

Matlab 与 modelsim 协同仿真的例程设置好modelsim运行环境后

proc vsimulink {args} {
  lappend sllibarg -foreign \{simlinkserver \{C:/MATLAB/toolbox/modelsim/windows32/simulinklink.dll\}
  if {[catch {lsearch -exact $args -socket} idx]==0  && $idx >= 0} {
    set socket [lindex $args [expr {$idx + 1}]]
    set args [lreplace $args $idx [expr {$idx + 1}]]
    append socketarg " \; -socket " "$socket"
    lappend sllibarg $socketarg
  }
  lappend sllibarg \}
  set args [linsert $args 0 vsim]
  lappend args [join $sllibarg]
  uplevel 1 [join $args]
}
proc vsimmatlab {args} {
  lappend mllibarg -foreign \{matlabclient \{C:/MATLAB/toolbox/modelsim/windows32/matlablink.dll\}
  lappend mllibarg \}
  lappend mlinput 
  lappend mlinput [join $args]
  lappend mlinput [join $mllibarg]
  set mlinput [linsert $mlinput 0 vsim]
  uplevel 1 [join $mlinput]
}
proc wrapverilog {args} {

  set nargs [llength $args]
  if {($nargs != 1) && ($nargs != 2)} {
      error "** Error: (wrapverilog) Wrong number of arguments; 
Usage is wrapverilog modulename or wrapverilog -nocompile modulename"
  }
  
  if {([lindex $args 0] == "-nocompile") && ($nargs == 2)} then {
      set modulename [lindex $args 1]
      set compileflag 0
  } elseif {$nargs == 1} {
      set modulename [lindex $args 0]
      set compileflag 1
  } else {
      error "** Error: (wrapverilog) Wrong arguments; 
Usage is wrapverilog modulename or wrapverilog -nocompile modulename"
  }

  set component [vgencomp $modulename]

  if {[string first "** Error:" $component] != -1} {
      error "** Error: (wrapverilog) ModelSim vgencomp cannot find module $modulename"
  }

  set modulename [string tolower $modulename]

  set fname "[string tolower $modulename]_wrap.vhd"

  set fid [open $fname w]

  if {$fid == -1} {
      error "** Error: (wrapverilog) Cannot open file $fname"
  }

  puts $fid "----------------------------------------------------------------"
  puts $fid "-- Module $modulename VHDL Wrapper"
  puts $fid "--"
  puts $fid "-- Generated by The MathWorks wrapverilog tcl command"
  puts $fid "--"
  puts $fid "-- Generated on: [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]"
  puts $fid "--"
  puts $fid "----------------------------------------------------------------"
  puts $fid "LIBRARY IEEE;"
  puts $fid "  USE IEEE.std_logic_1164.all;"
  puts $fid ""
  puts -nonewline $fid "ENTITY $modulename"
  puts $fid "_wrap IS"

  set firsteol [string first \n $component]
  set lasteol  [string last  \n $component]
  # Output generics and port map
  puts $fid [string range $component $firsteol $lasteol]

  puts -nonewline $fid "END $modulename"
  puts $fid "_wrap;"
  puts $fid ""
  puts -nonewline $fid "ARCHITECTURE rtl OF $modulename"
  puts $fid "_wrap IS"
  puts $fid ""
  puts $fid "$component"
  puts $fid ""
  puts $fid "FOR ALL : $modulename"
  puts -nonewline $fid "  USE ENTITY work.$modulename"
  puts $fid "(ignored);"
  puts $fid ""
  puts $fid "BEGIN"
  
  set portbeg [string first "port(" $component]
  if {$portbeg != -1} {
      puts $fid "  u_$modulename: $modulename"
      puts $fid "    PORT MAP ("
      set portmap [string range $component $portbeg $lasteol]
      set firsteol [string first \n $portmap]
      set portmap [string trimleft [string range $portmap $firsteol end]]

      set portnameend [string wordend $portmap 0]
      set portname [string range $portmap 0 $portnameend]
      set portname [string trimright $portname ":"]
      puts -nonewline $fid "      $portname => $portname"
      set firsteol [string first \n $portmap]	  
      set portmap [string trimleft [string range $portmap $firsteol end]]
      set errcnt 0
      while {([string length $portmap] != 0) &&
	     ([string index $portmap 0] != ")")} {
	  puts $fid ","
	  set portnameend [string wordend $portmap 0]
	  set portname [string range $portmap 0 $portnameend]
     set portname [string trimright $portname ":"]
	  puts -nonewline $fid "      $portname => $portname"
	  set firsteol [string first \n $portmap]	  
	  set portmap [string trimleft [string range $portmap $firsteol end]]
	  incr errcnt
	  if {$errcnt == 4096} {
	      error "** Error: (wrapverilog) Failure trying to parse more than 4096 ports for $modulename"
	  }
      }	  
      puts $fid ""
      puts $fid "    );"
  }
  puts $fid ""
  puts $fid "END rtl;"
  
  close $fid

  if {$compileflag} {
      uplevel 1 vcom $fname
  }
}

cd C:/MATLAB/toolbox/modelsim/modelsimdemos/vhdl/manchester
catch {wm geometry . 500x200+0+0}
vlib work
vcom -performdefaultbinding C:/MATLAB/toolbox/modelsim/modelsimdemos/vhdl/manchester/decoder.vhd
vsimmatlab work.decoder
matlabtb decoder -mfunc Manchester_decoder -socket 1037
run 3000
quit -f