st20c2_c200chip.cfg

flash programming STI 5.5.1.4 DCU3

include commonchip.cfg
include ST20C2_C200addr.cfg

DCU_base = (Devices[Devices.DCUindex].addr)

## Setup default values for DCU3 capability and sequencing register values.
## Actual values read from DCU3 hardware.
##
DCU3_capability = 0x20022121
DCU3_sequencing = 0x01212121

include dcu3.cfg

proc st20c2_c200_registers {
  dcu3_registers (Devices[Devices.DCUindex].addr)
  InterruptControllerNLevelsRegisters (Devices[Devices.INTCTRLindex].addr, Devices[Devices.INTCTRLLEVELSindex].addr)
  CacheControl3Registers (Devices[Devices.ICACHEindex].addr, 1)
  CacheControl3Registers (Devices[Devices.DCACHEindex].addr, 0)
}


proc st20c2_c200_map {
  memory INTERNAL 0x80000000 (8*K) RAM 
  memory SYSTEM   0x80000000 (0x140) RESERVED
  memory INT_CONTROLLER (Devices[Devices.INTCTRLindex].addr)  0x400  PERIPHERAL
  memory DCU            (Devices[Devices.DCUindex].addr)      0x1000 DEVICE  
  memory ICacheControl  (Devices[Devices.ICACHEindex].addr)   0x1000 DEVICE
  memory DCacheControl  (Devices[Devices.DCACHEindex].addr)   0x1000 DEVICE

## Addresses are aliased between the INT_CONTROLLER and INTC_MIRROR segments.
## This is to allow for future expansion of the interrupt controller
## and to also support backwards compatibility.

  memory INTC_MIRROR    (Devices[Devices.INTCTRLMIRRORindex].addr) \
                                                              0x3000 RESERVED
}


proc st20c2_c200_chip {
  dcu3_c2
  st20c2_c200_map
  st20c2_c200_registers
}