chip.cfg

flash programming STI 5.5.1.4 DCU3

    _ST_local_ret = 0 
  }
  $$ = _ST_local_ret
}

proc _ST_ReadProductId _ST_local_ret {
  $$ = (((_ST_ReadDeviceId) >> 12) & ((1<<16)-1))
}

proc _ST_ProcessorSetup _ST_local_chip _ST_local_index _ST_local_prodid _ST_local_retval {
  ## $1 is the product id
  ## $2 is the core type 

  _ST_local_retval = 0
  _ST_local_prodid = mknum($1) 

  ## prodid==0 for simulator targets 
  if ($2=="st20c2") {
    ST20C2CPU
  } else {
    ST20C1CPU
  }

  if ( _ST_local_prodid!=0 ) {

    ## check for existance in the prodid list
    _ST_local_chip = "" 
    for (_ST_local_index=0; _ST_local_index<_ST_global_ProdidList.count; _ST_local_index++ ) {
      if (_ST_global_ProdidList[_ST_local_index] == _ST_local_prodid) {
        _ST_local_chip = _ST_global_ProdidToChipNameMap[_ST_local_prodid]
      }
    }
  
    ## if we have found a matching prodid, set up essential chip specific things 
    if (_ST_local_chip != "") {

      CacheControlProc[spaceid] = (_ST_global_ChipNameMap[_ST_local_chip][_ST_global_ChipIndex_cacheControl])
      DCUBase[spaceid]          = (_ST_global_ChipNameMap[_ST_local_chip][_ST_global_ChipIndex_dcuBase])
      DCUType[spaceid]          = (_ST_global_ChipNameMap[_ST_local_chip][_ST_global_ChipIndex_dcuType])

      ## If the chip has a DCU3, pick the appropriate dcu3 traphandler
      ## For backwards compatibility we normally instantiate a basic cXtrap.bin
      ## when using the processor command but such a traphandler would be
      ## useless on a DCU3 part
      if ((DCUType[spaceid]<<4)=="DCU3") {
        _ST_global_dcuCheck = 1
        TrapHandler[spaceid] = ("dcu3" + TrapHandler[spaceid])
      }

      _ST_local_retval = 1 ;
    } else {
      _ST_local_retval = 0 ;
    }
  }

  ## linker definitions for DCU type
  _ST_DefineDCUType

  $$ = _ST_local_retval
}   

proc chip _ST_local_index \
  _ST_local_found \
  _ST_local_prodid \
  _ST_local_mask \
  _ST_local_masked_prodid \
  _ST_local_masked_expprodid  {
  ## $1 is the chip name

  ## ensure we have got a chip name matching the supplied name
  ## do it with this separate name list because there is a command language deficiency
  ## which prevents the use of 'if (clsymbol _ST_global_ProdidToChipNameMap[$1]) ...'

  _ST_local_found = 0 
  for (_ST_local_index=0; _ST_local_index<_ST_global_NameList.count ;_ST_local_index++ ) {
    if (_ST_global_NameList[_ST_local_index] == $1) {
      _ST_local_found = 1
    }
  }

  if (_ST_local_found) {

    ## do the processor setup 

    if (_ST_ProcessorSetup  (_ST_global_ChipNameMap[$1].prodid) (_ST_global_ChipNameMap[$1].coreType)) {
      $$ = 1 
    } else {
      $$ = 0 
    }

    ## execute the chip procedure
    parse ("include " + _ST_global_ChipNameMap[$1][_ST_global_ChipIndex_configFile])
    parse (_ST_global_ChipNameMap[$1][_ST_global_ChipIndex_configProc])

    ## provide linker config. scripts (eg -runtime os20) access to the chip name
    _ST_global_ChipName[spaceid]=$1

    OS20_config.chip_variant=$1
    ## These must be defined for OS/20
    if (! (clsymbol Devices.INTCTRLindex)) {
      define InterruptControllerAddr% 0
      define InterruptControllerLevels% 0
    }
    if (! (clsymbol Devices.INTLEVELCTRLindex)) {
      define InterruptLevelControllerAddr% 0
      define InterruptLevelControllerNumInputs% 0
      define InterruptLevelControllerInputOffset% 0
    }

    ## define all the register names
    for (i=0;i<Devices.index;i++) {
      define ((Devices[i].symname)+"%") (Devices[i].addr)
      if(clsymbol ST_reg_debug) {write "Device " (Devices[i].symname) " @ " -x (Devices[i].addr)}
    }

    ## setup chip specific traphandler
    TrapHandler[spaceid] = _ST_global_ChipNameMap[$1][_ST_global_ChipIndex_trapHandler]

    ## warn if we are using st20run and the actual prodid mismatches the value in the lookup table
    if ((clsymbol trace)==3) {
      if (_ST_global_DevidOverride!=-1) {
        ## we want to supply the devid instead of extracting it from the target
        _ST_local_prodid = ((_ST_global_DevidOverride) >> 12) & ((1<<16)-1)
      } else {
        _ST_local_prodid = (_ST_ReadProductId)
      }

      _ST_local_mask             = (~mknum (_ST_global_ChipNameMap[$1][_ST_global_ChipIndex_prodidMask]))
      _ST_local_masked_prodid    = (_ST_local_prodid & _ST_local_mask)
      _ST_local_masked_expprodid = ((_ST_global_ChipNameMap[$1].prodid) & _ST_local_mask)

      if ( (_ST_local_masked_prodid != 0 ) && \
           (_ST_local_masked_expprodid != 0) && \
           (_ST_local_masked_prodid != _ST_local_masked_expprodid ) ) {
        write ("Warning: the product id specified in the lookup table, " + (mkstr -x (_ST_global_ChipNameMap[$1].prodid)) + \
               ", does not match the product id extracted from the device, " + (mkstr -x (_ST_local_prodid)) )
      }
    }
  } else {
    clerror ("unsupported chiptype " + $1)
  }
}   
  
proc processor \
  _ST_local_coretype \
  _ST_local_prodid \
  _ST_local_loop \
  _ST_local_errString \
  _ST_local_coreString \
{
  if ($#<1) {
    clerror ("processor command takes one argument" )  
  }

  _ST_local_coretype = $1 

  if ($#>1) {
    _ST_local_errString = "Unsupported options: processor"
    for (_ST_local_loop=1; _ST_local_loop<=$#; _ST_local_loop++) {
      _ST_local_errString += ( " " + $(_ST_local_loop) )
    }
    clerror ( _ST_local_errString )
  }
  
  if (_ST_local_coretype == "c1" || _ST_local_coretype == "C1" || _ST_local_coretype == "st20c1") {
    _ST_local_coreString = "st20c1" 
  } else if (_ST_local_coretype == "c2" || _ST_local_coretype == "C2" || _ST_local_coretype == "st20c2") {
    _ST_local_coreString = "st20c2" 
  } else {
    _ST_local_coreString = "" 
  }

  if (_ST_local_coreString != "" ) {
     
    if (_ST_global_DevidOverride!=-1) {
      ## we want to suplpy the devid instead of extracting it from the target
      _ST_local_prodid = ((_ST_global_DevidOverride) >> 12) & ((1<<16)-1)
    } else {
      _ST_local_prodid = (_ST_ReadProductId)
    }
    _ST_global_dcuCheck = 0
    if ((_ST_ProcessorSetup (_ST_local_prodid) (_ST_local_coreString))==0) {
      if ((_ST_ReadDeviceId)!=0) {
        ## device id of 0 for a hosted space
        ## TapMonitor checks for an id of 0 on silicon so it will
        ## generate an error if necessary before this point is reached
        write Warning: unrecognised device ID -x (_ST_local_prodid)
        write This may cause breakpoint and stepping failures with code in RAM when the I cache is enabled
      }
    }
    if (_ST_global_dcuCheck == 1) {
       write  Warning: processor command used with a DCU3 device. Use the chip command instead.
    }
  } else {
    clerror ("unsupported coretype " + _ST_local_coretype)
  }
}

## The product id is bits 28..12 of the processor's 32 bit device id.
## Device ids of supported processors are listed below.
  
## ST20DC1              0x05177041
## ST20DC2              0x05178041
## STi5500H5            0x050c9041
## STi5500              0x1d4c9041
## STi5505              0x3d4cb041
## STi5508              0x1d402041
## STi5580              0x1d40b041
## STi5588              0x1d41c041
## STi5519              0x1d415041
## STi5510              0x2d4cd041
## STi5512S             0x1d401041
## STi5512A             0x3d406041
## STi5512M             0x3d407041
## STi5512N             0x00000000
## STi5514              0x1d40a041
## STi5516              0xXd41d041
## STi5518              0x1d405041
## ST20TP3              0x05194041
## ST20TP4              0x25198041
## ST20GP6              0x15196041 
## ST20MC2              0x05195041
## ST20C200_EMUL        0x05000011
## STV0396              0x05003041
## STV3500              0x051C0041

##            chipName          prodid Mask   coreType  cacheContro       interruptControl dcuType  dcuBase   trapType trapHandler        configFile              configProc     IntC/ILC cacheMap   

_ST_AddDevice "STi5500H5"       0x50c9 0x0000 "st20c2" "CacheControl5500" "C2Interrupts" "DCU2H5" (0x3000)     "c2th" "5500c1trap.bin"   "STi5500chip.cfg"       "sti5500chip"      1 1 "cache_map_sti5500%os"
_ST_AddDevice "STi5500"         0xd4c9 0x0000 "st20c2" "CacheControl5500" "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "5500c2_2trap.bin" "STi5500chip.cfg"       "sti5500chip"      1 1 "cache_map_sti5500%os"
_ST_AddDevice "STi5505"         0xd4cb 0x0000 "st20c2" "CacheControl5500" "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "5500c2_2trap.bin" "STi5505chip.cfg"       "sti5505chip"      1 1 "cache_map_sti5500%os"
_ST_AddDevice "STi5508"         0xd402 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5508chip.cfg"       "sti5508chip"      1 1 "cache_map_sti5510%os"
_ST_AddDevice "STi5510"         0xd4cd 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5510chip.cfg"       "sti5510chip"      1 1 "cache_map_sti5510%os"
_ST_AddDevice "STi5512"         0xd401 0x000f "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5512chip.cfg"       "sti5512chip"      1 1 "cache_map_sti5512%os"     
_ST_AddDevice "STi5512S"        0xd401 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5512chip.cfg"       "sti5512chip"      1 1 "cache_map_sti5512%os"
_ST_AddDevice "STi5512A"        0xd406 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5512chip.cfg"       "sti5512chip"      1 1 "cache_map_sti5512%os"
_ST_AddDevice "STi5512M"        0xd407 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5512chip.cfg"       "sti5512chip"      1 1 "cache_map_sti5512%os"
_ST_AddDevice "STi5512N"        0xd408 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5512chip.cfg"       "sti5512chip"      1 1 "cache_map_sti5512%os"
_ST_AddDevice "STi5514"         0xd40a 0x0000 "st20c2" "CacheControlC200" "C2Interrupts" "DCU3"   (0x30003000) "c2th" "5514trap.bin"     "STi5514chip.cfg"       "sti5514chip"      1 3 "cache_map_c2_c200%os"
_ST_AddDevice "STi5516"         0xd41d 0x0000 "st20c2" "CacheControlC200" "C2Interrupts" "DCU3"   (0x30003000) "c2th" "5514trap.bin"     "STi5514chip.cfg"       "sti5514chip"      1 3 "cache_map_c2_c200%os"  ## Sti5516 is variant of STi5514
_ST_AddDevice "STi5517"         0xd41F 0x0000 "st20c2" "CacheControlC200" "C2Interrupts" "DCU3"   (0x30003000) "c2th" "5514trap.bin"     "STi5514chip.cfg"       "sti5514chip"      1 3 "cache_map_c2_c200%os"  ## Sti5516 is variant of STi5514
_ST_AddDevice "STi5518"         0xd405 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5518chip.cfg"       "sti5518chip"      1 2 "cache_map_sti5512%os"
_ST_AddDevice "STi5519"         0xd415 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5518chip.cfg"       "sti5518chip"      1 2 "cache_map_sti5512%os"  ## STi5519 is variant of STi5518
_ST_AddDevice "STi5580"         0xd40b 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5508chip.cfg"       "sti5508chip"      1 1 "cache_map_sti5510%os"  ## STi5580 is variant of STi5508
_ST_AddDevice "STi5588"         0xd41c 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "STi5518chip.cfg"       "sti5518chip"      1 2 "cache_map_sti5512%os"  ## STi5588 is variant of STi5518
_ST_AddDevice "ST20DC1"         0x5177 0x0000 "st20c1" "CacheControlDC1"  "C1Interrupts" "DCU2H6" (0x3000)     "c1th" "c1trap.bin"       "ST20DC1chip.cfg"       "dc1chip"          2 1 "cache_map_st20dc1%os"
_ST_AddDevice "ST20DC2"         0x5178 0x0000 "st20c1" "CacheControlDC1"  "C1Interrupts" "DCU2H6" (0x3000)     "c1th" "c1trap.bin"       "ST20DC1chip.cfg"       "dc1chip"          2 1 "cache_map_st20dc1%os"
_ST_AddDevice "ST20MC2"         0x5195 0x0000 "st20c1" "_ST_dummyproc"    "C1Interrupts" "DCU2H5" (0x3000)     "c1th" "c1trap.bin"       "ST20MC2chip.cfg"       "mc2chip"          1 1 ""
_ST_AddDevice "ST20TP3"         0x5194 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "ST20TP3chip.cfg"       "tp3chip"          1 1 "cache_map_st20tp3%os"
_ST_AddDevice "ST20TP4"         0x5198 0x0000 "st20c2" "CacheControlTP3"  "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "tp3trap.bin"      "ST20TP3chip.cfg"       "tp3chip"          1 1 "cache_map_st20tp3%os"
_ST_AddDevice "ST20GP6"         0x5196 0x0000 "st20c2" "_ST_dummyproc"    "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "c2trap.bin"       "ST20GP6chip.cfg"       "gp6chip"          1 1 ""
_ST_AddDevice "STV0396"         0x5003 0x0000 "st20c2" "CacheControlC200" "C2Interrupts" "DCU3"   (0x30003000) "c2th" "396trap.bin"      "STV0396chip.cfg"       "STV0396_chip"     1 2b "cache_map_c2_c200%os"
_ST_AddDevice "STV3500"         0x51c0 0x0000 "st20c2" "CacheControlC200" "C2Interrupts" "DCU3"   (0x30003000) "c2th" "dcu3c2trap.bin"   "STV3500chip.cfg"       "stv3500chip"      1 3 "cache_map_c2_c200%os"

_ST_AddDevice "ST20C1SIM"       0      0x0000 "st20c1" "_ST_dummyproc"    "C1Interrupts" "DCU2H6" (0x3000)     "c1th" "c1trap.bin"       "ST20C1SIMchip.cfg"     "c1simchip"        1 0 ""
_ST_AddDevice "ST20C2SIM"       0      0x0000 "st20c2" "_ST_dummyproc"    "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "c2trap.bin"       "ST20C2SIMchip.cfg"     "c2simchip"        1 0 ""
_ST_AddDevice "ST20C2SIM_BANK0" 0      0x0000 "st20c2" "_ST_dummyproc"    "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "c2trap.bin"       "ST20C2SIMchip.cfg"     "c2simchip 0"      1 0 ""
_ST_AddDevice "ST20C2SIM_BANK1" 0      0x0000 "st20c2" "_ST_dummyproc"    "C2Interrupts" "DCU2H6" (0x3000)     "c2th" "c2trap.bin"       "ST20C2SIMchip.cfg"     "c2simchip 1"      1 0 ""
_ST_AddDevice "ST20DCU3C1SIM"   0      0x0000 "st20c1" "_ST_dummyproc"    "C1Interrupts" "DCU3"   (0x30003000) "c1th" "dcu3c1trap.bin"   "ST20DCU3C1SIMchip.cfg" "dcu3c1simchip"    1 0 ""
_ST_AddDevice "ST20DCU3C2SIM"   0      0x0000 "st20c2" "_ST_dummyproc"    "C2Interrupts" "DCU3"   (0x30003000) "c2th" "dcu3c2trap.bin"   "ST20DCU3C2SIMchip.cfg" "dcu3c2simchip"    1 0 ""