st20dc1addr.cfg

flash programming STI 5.5.1.4 DCU3

## ###########################################################################
## Copyright (c) STMicroelectronics 2000
## 
## Date: 2000/04/05 $
## Author: panesarg edited by threlfall
## Purpose: List of the DC1 peripherals with base address and interrupt
##          numbers
## ###########################################################################

if (!(clsymbol DC1ADDR)) {
DC1ADDR=1

##
## Base addresses
##

##{{{  IMAGE PROCESSING subsystem

JPEGBASE                = 0x20040000  ## ST
JPEGSIZE                = 0x00010000

##}}}
##{{{  System service subsystem

RTCBASE                 = 0x20030000 ## ST
RTCSIZE                 = 0x00000040 ## ST
POWERMANAGEBASE         = 0x20030040 ## ST
POWERMANAGESIZE         = 0x00000040 ## ST

##}}}
##{{{  Transport subsystem

BLOCKMOVEBASE           = 0x20028000 ## ST
BLOCKMOVESIZE           = 0x00008000 ## ST

##}}}
##{{{  Comms subsystem

ASC0BASE                = 0x20010000  ## ST
ASC0SIZE                = 0x00000080

ASC1BASE                = 0x20010080  ## ST
ASC1SIZE                = 0x00000080

SSC0BASE                = 0x20010100  ## ST
SSC0SIZE                = 0x00000080

SSC1BASE                = 0x20010180  ## ST
SSC1SIZE                = 0x00000080

SSC2BASE                = 0x20010200  ## ST
SSC2SIZE                = 0x00000080

I1394LLIBASE            = 0x20010280  ## ST
I1394LLISIZE            = 0x00000080

PIOBASE			= 0x20010300  ## ST
PIOSIZE			= 0x00000080

##}}}
##{{{  CPU Core subsystem
INTERRUPTLEVELBASE      = 0x20000000 ## ST
INTERRUPTLEVELSIZE      = 0x00000200

INTERRUPTBASE           = 0x20000200 ## ST
INTERRUPTSIZE           = 0x00000200

PWMBASE                 = 0x20000400 ## ST
PWMSIZE                 = 0x00000200
##}}}

##{{{  Cache control registers
CACHECONTROLBASE        = 0x20000600
CACHECONTROLSIZE        = 0x00001000
##}}}

##{{{  EMI/FMI
EMI3CONFIGBASE                = 0xC8000000 ## ST
EMI3CONFIGSIZE                = 0x00000080
FMICONFIGBASE                 = 0x40400000 ## ST
FMICONFIGSIZE                 = 0x00000080
##}}}

##
## Peripherals defined by chip command
##

Devices.index=0

Devices.JPEGindex=Devices.index++
Devices[Devices.JPEGindex].symname = "JPEGAddr"
Devices[Devices.JPEGindex].addr = (JPEGBASE)

Devices.RTCindex=Devices.index++
Devices[Devices.RTCindex].symname = "RTCAddr"
Devices[Devices.RTCindex].addr = (RTCBASE)

Devices.LPCTRLindex=Devices.index++
Devices[Devices.LPCTRLindex].symname = "LowPowerControllerAddr"
Devices[Devices.LPCTRLindex].addr = (POWERMANAGEBASE)

Devices.BlockMoveindex=Devices.index++
Devices[Devices.BlockMoveindex].symname = "BlockMoveDMAControllerAddr"
Devices[Devices.BlockMoveindex].addr = (BLOCKMOVEBASE)

Devices.ASC0index=Devices.index++
Devices[Devices.ASC0index].symname = "ASC0Addr"
Devices[Devices.ASC0index].addr = (ASC0BASE)

Devices.ASC1index=Devices.index++
Devices[Devices.ASC1index].symname = "ASC1Addr"
Devices[Devices.ASC1index].addr = (ASC1BASE)

Devices.SSC0index=Devices.index++
Devices[Devices.SSC0index].symname = "SSC0Addr"
Devices[Devices.SSC0index].addr = (SSC0BASE)

Devices.SSC1index=Devices.index++
Devices[Devices.SSC1index].symname = "SSC1Addr"
Devices[Devices.SSC1index].addr = (SSC1BASE)

Devices.SSC2index=Devices.index++
Devices[Devices.SSC2index].symname = "SSC2Addr"
Devices[Devices.SSC2index].addr = (SSC2BASE)

Devices.IEEE1394index=Devices.index++
Devices[Devices.IEEE1394index].symname = "IEEE1394LLIAddr"
Devices[Devices.IEEE1394index].addr = (I1394LLIBASE)

Devices.PIOindex=Devices.index++
Devices[Devices.PIOindex].symname = "PIOControllerAddr"
Devices[Devices.PIOindex].addr = (PIOBASE)

Devices.INTLEVELCTRLindex=Devices.index++
Devices[Devices.INTLEVELCTRLindex].symname = "InterruptLevelControllerAddr"
Devices[Devices.INTLEVELCTRLindex].addr = (INTERRUPTLEVELBASE)

Devices.INTLEVELCTRLNUMINPUTSindex=Devices.index++
Devices[Devices.INTLEVELCTRLNUMINPUTSindex].symname = "InterruptLevelControllerNumInputs"
Devices[Devices.INTLEVELCTRLNUMINPUTSindex].addr = 24

Devices.INTLEVELCTRLINPUTOFFSETindex=Devices.index++
Devices[Devices.INTLEVELCTRLINPUTOFFSETindex].symname = "InterruptLevelControllerInputOffset"
Devices[Devices.INTLEVELCTRLINPUTOFFSETindex].addr = 31

Devices.INTCTRLindex=Devices.index++
Devices[Devices.INTCTRLindex].symname = "InterruptControllerAddr"
Devices[Devices.INTCTRLindex].addr = (INTERRUPTBASE)

Devices.INTCTRLLEVELSindex=Devices.index++
Devices[Devices.INTCTRLLEVELSindex].symname = "InterruptControllerLevels"
Devices[Devices.INTCTRLLEVELSindex].addr = 8

Devices.PWMCTRLindex=Devices.index++
Devices[Devices.PWMCTRLindex].symname = "PWMControllerAddr"
Devices[Devices.PWMCTRLindex].addr = (PWMBASE)

Devices.EMIindex=Devices.index++
Devices[Devices.EMIindex].symname = "EMIAddr"
Devices[Devices.EMIindex].addr = (EMI3CONFIGBASE)

Devices.FMIindex=Devices.index++
Devices[Devices.FMIindex].symname = "FMIAddr"
Devices[Devices.FMIindex].addr = (FMICONFIGBASE)

Devices.CACHEindex=Devices.index++
Devices[Devices.CACHEindex].symname = "CacheControlAddr"
Devices[Devices.CACHEindex].addr = (CACHECONTROLBASE)

}