st20dcu3c2simchip.cfg

flash programming STI 5.5.1.4 DCU3

include commonchip.cfg
include ST20C2SIMaddr.cfg
include dcu3.cfg

proc dcu3c2simregisters i=0 {
  EMIRegisters (Devices[Devices.EMIindex].addr, true, true, "c2sim")
  dcu3_registers (Devices[Devices.DCU2index].addr)
  InterruptControllerRegisters (Devices[Devices.INTCTRLindex].addr)
}

proc c2sim_core_memory {
  memory INTERNAL 0x80000000 (4*K) RAM 
  memory SYSTEM   0x80000000 (0x140) RESERVED
  memory DCU            (DCU_base) 0x1000 DEVICE       ## can be word accessed via DCU 
  memory INT_CONTROLLER 0x20000000 0x1000 PERIPHERAL   ## cannot be accessed via DCU
  memory EMI            0x20002000 0x1000 PERIPHERAL   ## cannot be accessed via DCU
}


proc dcu3c2simchip {
  dcu3_c2
  c2sim_core_memory
  dcu3c2simregisters
}