st20dc1chip.cfg

来自「flash programming STI 5.5.1.4 DCU3」· CFG 代码 · 共 171 行

## ###########################################################################
## Copyright (c) STMicroelectronics 2000
## 
## Date: 2000/04/05 $
## Author: panesarg edited by threlfall & thompsond
## Purpose: List of the DC1 peripherals with base address and interrupt
##          numbers
## ###########################################################################

include commonchip.cfg
include ST20DC1addr.cfg

##{{{  defines
K                	= 1024
M                	= (K * K)
##}}}

##
## Memory segments placed here so that they can be picked up
## by the makefile
##

INTERNALBASE            = (0x80000000)
INTERNALSIZE            = (0x2000)

SDRAMSIZE        	= (0x2000000)
SDRAMBASE	  	= (0xC0000000)

FLASHBASE        	= (0x40000000)
FLASHSIZE               = (0x100000)


##
## Application dependent defines
## (not really part of the model)
##


SYSTEMPARTSIZE        = (0x10000)
SYSTEMPARTBASE        = (SDRAMBASE)

INTERNALPARTSIZE      = (0x10000)
INTERNALPARTBASE      = (SYSTEMPARTBASE + SYSTEMPARTSIZE)

SIGNATURESIZE         = (0x1000)
SIGNATUREBASE         = (SDRAMBASE + SDRAMSIZE - SIGNATURESIZE)

SPARESDRAMBASE        = (INTERNALPARTBASE + INTERNALPARTSIZE)
SPARESDRAMSIZE        = (SDRAMSIZE - INTERNALPARTSIZE - SYSTEMPARTSIZE - SIGNATURESIZE)

## MUST match the contents of st20dc1.h

C1RESERVEDSIZE        = (0x080)
C1RESERVEDBASE        = (INTERNALBASE)

SPAREINTERNALSIZE        = (INTERNALSIZE - C1RESERVEDSIZE)
SPAREINTERNALBASE        = (C1RESERVEDBASE + C1RESERVEDSIZE)

proc dc1memory {
  memory C1RESERVED         (C1RESERVEDBASE)       (C1RESERVEDSIZE)       RESERVED
  memory INTERNAL           (SPAREINTERNALBASE)    (SPAREINTERNALSIZE)    RAM

  memory INTERRUPT          (INTERRUPTBASE)        (INTERRUPTSIZE)        DEVICE
  memory ASC0               (ASC0BASE)             (ASC0SIZE)             DEVICE
  memory ASC1               (ASC1BASE)             (ASC1SIZE)             DEVICE
  memory SSC0               (SSC0BASE)             (SSC0SIZE)             DEVICE
  memory SSC1               (SSC1BASE)             (SSC1SIZE)             DEVICE
  memory SSC2               (SSC2BASE)             (SSC2SIZE)             DEVICE
  memory I1394LLI           (I1394LLIBASE)         (I1394LLISIZE)         DEVICE
  memory PIO                (PIOBASE)              (PIOSIZE)              DEVICE
  memory JPEG               (JPEGBASE)             (JPEGSIZE)             DEVICE
  memory RTC                (RTCBASE)              (RTCSIZE)              DEVICE
  memory POWERMANAGE        (POWERMANAGEBASE)      (POWERMANAGESIZE)      DEVICE
  memory INTERRUPTLEVEL     (INTERRUPTLEVELBASE)   (INTERRUPTLEVELSIZE)   DEVICE
  memory PWM                (PWMBASE)              (PWMSIZE)              DEVICE
  memory CACHECONTROL       (CACHECONTROLBASE)     (CACHECONTROLSIZE)     DEVICE
  memory BLOCKMOVE          (BLOCKMOVEBASE)        (BLOCKMOVESIZE)        DEVICE
  memory FMICONFIG          (FMICONFIGBASE)        (FMICONFIGSIZE)        DEVICE
  memory EMI3CONFIG         (EMI3CONFIGBASE)       (EMI3CONFIGSIZE)       DEVICE
}

proc dc1registers i=0 {
  ## JPEGRegisters (Devices[Devices.JPEGindex].addr)
  RTCRegisters (Devices[Devices.RTCindex].addr, "dc1")
  PeripheralPowerControllerRegisters (Devices[Devices.LPCTRLindex].addr, "dc1")
  BlockMoveDMAControllerRegisters (Devices[Devices.BlockMoveindex].addr)
  AsynchronousSerialControllerRegisters (Devices[Devices.ASC0index].addr, 0, true, true, "dc1")
  AsynchronousSerialControllerRegisters (Devices[Devices.ASC1index].addr, 1, true, true, "dc1")
  SynchronousSerialController2Registers (Devices[Devices.SSC0index].addr, 0)
  SynchronousSerialController2Registers (Devices[Devices.SSC1index].addr, 1)
  SynchronousSerialController2Registers (Devices[Devices.SSC2index].addr, 2)
  PIOControllerRegisters (Devices[Devices.PIOindex].addr, 0)
  InterruptLevelControllerRegisters (Devices[Devices.INTLEVELCTRLindex].addr, Devices[Devices.INTLEVELCTRLNUMINPUTSindex].addr, true, false)
  InterruptController2Registers (Devices[Devices.INTCTRLindex].addr, Devices[Devices.INTCTRLLEVELSindex].addr, false)
  ExceptionVectorTableRegisters (0x80000040, Devices[Devices.INTCTRLLEVELSindex].addr)
  PWMControllerRegisters (Devices[Devices.PWMCTRLindex].addr)
  EMIRegisters (Devices[Devices.EMIindex].addr, true, false, "dc1")
  EMIRegisters (Devices[Devices.FMIindex].addr, true, false, "dc1", "FMI")
  CacheControl3Registers (Devices[Devices.CACHEindex].addr, true)
}

proc dc1chip {
  dc1memory
  dc1registers
}

HUNDRED_MS           = 100
LP_CONFIG_RUN_SLOW   = ((1 << 0) || (1 << 1))
LP_CONFIG_RUN_FAST   = ((1 << 0) || (1 << 1))
CLOCK_MODE_STANDBY   = 1
CLOCK_MODE_RUN_SLOW  = 2
CLOCK_MODE_RUN_FAST  = 3
TRUE                 = 1
FALSE                = 0

## Procedure to move DC1 from fast to standby

proc RunFastToStandby {
  poke ((RTCBASE)+0x00) (CLOCK_MODE_STANDBY)
  ##RtcRegister->ClockMode = CLOCK_MODE_STANDBY;
}

## Procedure to move DC1 from fast to standby

proc ST20DC1RunSlowToFast {
  poke ((RTCBASE)+0x00) (CLOCK_MODE_RUN_FAST)
  ##RtcRegister->ClockMode = CLOCK_MODE_RUN_FAST;
}


## Procedure to move DC1 from standby to run fast mode

proc ST20DC1StandbyToRunFast {
  ## Turn on the 27Mhz oscillator 
  poke ((POWERMANAGEBASE)+0x30) 1 
  ##PowerManageRegister->OscEnable = 1;

  ## Enable rtc power supplies ##
  poke ((RTCBASE)+0x04) (LP_CONFIG_RUN_FAST)
  ##RtcRegister->LPConfig = LP_CONFIG_RUN_FAST;
  
  ## Wait 100 ms 
  for (ii = 0 ; ii < (HUNDRED_MS) ; ii++) 

  ##{
  ##  volatile int i;
  ##  for (i = 0; i < HUNDRED_MS; i++);
  ##}

  ## Enable Pll 
  poke ((POWERMANAGEBASE)+0x24) 1
  ##PowerManageRegister->PllEnable = 1;

  PllNotLocked = TRUE

  ## Wait PLL lock 
  while (PllNotLocked) {
    ## Two successive read in PllLocked with result 1
    ##   means PLL locked 
    if (((peek -q ((POWERMANAGEBASE)+(0x24))) & 1) == 1) {
      if (((peek -q ((POWERMANAGEBASE)+(0x24))) & 1) == 1) {
	PllNotLocked = FALSE 
      }
    }
  }
  
  ## Move to run fast (program the rtc) 
  poke ((RTCBASE)+0x00) (CLOCK_MODE_RUN_FAST)
  ##RtcRegister->ClockMode = CLOCK_MODE_RUN_FAST;
}