board.cfg

flash programming STI 5.5.1.4 DCU3

################################################################################
## vi:sw=2 ts=2 et:
## 
## File: $RCSfile: board.cfg,v $
##       $Revision: 1.45 $
##       $Date: 2002/10/22 10:31:27 $
##            
## Copyright [2001] Pace Micro Technology PLC.   All rights reserved.
## 
## The copyright in this material is owned by Pace Micro Technology PLC
## ("Pace"). This material is regarded as a highly confidential trade secret of
## Pace. It may not be reproduced, used, sold or in any other way exploited or
## transferred to any third party without the prior written permission of Pace.
## 
################################################################################

###############################################################################
############## LOW LEVEL PROCEDURES ########################################
###############################################################################

####################################################
## EMI MEMORY MAP
####################################################
## BANK0 0x40000000-0x41FFFFF0 SDRAM        (32 MB)
## BANK1 0x50000000-0x5FFFFFFF Not used
## BANK2 0x60000000-0x6FFFFFFF HSDP         (256 MB)
## BANK3 0x70000000-0x7DFFFFFF Not used				         
## BANK4 0x7F400000-0x7F800000 FLASH        (4 MB)
## BANK5 0x7FC00000-0x7FFFFFFF FLASH        (4 MB)
####################################################
## SDRAM for STI5514, Single 64Mbit device (4 Banks)
## for initialisation to be provided, clocks must be running, but the speed
## of the SDRAM depends of the PLL, we use 112.5MHz [SJBA]

################################################################################
## MemoryMap_Defines()
## Define the physical memory map values/locations of the board. 
## Lowest level cfg procedure.
##    called by   Board_MemoryMap(), Board_MemoryMap_WithLoader  ie main drivers
##     and        Board_MemoryMap_boot()  ie hostboot/romboot

proc MemoryMap_Defines {

  #####################
  ## SMI AV SDRAM 
  AV_SDRAM_ADDR         = 0xC0000000
  AV_SDRAM_SIZE         = (8*M) 
  AVSDRAM_BUS_WIDTH     = 16

  #####################
  ## EMI SDRAM 
  EMI0_ADDR             = 0x40000000
  EMI0_SIZE             = (32*M)
  EMISDRAM_BUS_WIDTH    = 32
    
## below HSDP and PORT_EXP lifted from Sabre, but probably not correct yet

  #####################
  ## HIGH SPEED DATA PORT 
  HSDP_ADDR             = 0x60000000
  HSDP_SIZE             = (256*M)
  
  #####################
  ## FPGA
  FPGA_ADDR					= 0x60200000
  FPGA_SIZE					= (64*K)

  #####################
  ## PORT EXPANDER
  PORT_EXP_ADDR         = 0x60000000
  PORT_EXP_SIZE         = (2*M)

  #####################
  ## FLASH organisation

  FLASH_BANK1_ADDR      = 0x7F400000
  FLASH_BANK0_ADDR      = 0x7FC00000
    
  FLASH_BANK_SIZE       = (4*M) 
  FLASH_BANK_SPACE      = (1* FLASH_BANK_SIZE)
  FLASH_TOP_MARGIN		= (256*K)

## RT020902 size of flash header as defined by OpenTV
  FLASH_HDR_SIZE  		= 36

  FLASH_NORMAL_ADDR     = (FLASH_BANK0_ADDR) + (FLASH_BANK_SPACE) - (FLASH_BANK_SIZE)
  FLASH_MIRROR_ADDR     = (FLASH_BANK1_ADDR) + (FLASH_BANK_SPACE) - (FLASH_BANK_SIZE)
## FLASH_NORMAL_SIZE	    = we cannot set this here since we might(or not) want 
##                        hostboot AND OR LOADER. It'll be set by CALLING procedure.
  
##write Flash Bank0 addr       = -x (FLASH_BANK0_ADDR)
##write Flash Bank size        = -d (FLASH_BANK_SIZE)
##write Flash normal ADDR      = -x (FLASH_NORMAL_ADDR)
##write Flash mirror ADDR      = -x (FLASH_MIRROR_ADDR)

}
## end MemoryMap_Defines() ##

################################################################################
## Loader specific defines - MemoryMap_Defines MUST have been called prior
## to this.   however, it is not always pertinent to call from here, so
## this is not done
################################################################################
proc Loader_MemDefs {

  ##################################################################################
  ## RT210502
  ## these defines mark the start and end of the two write-protected areas
  ##################################################################################
  define cfg_loader_bank0_start   (LDRFLASH_NORMAL_ADDRESS)
  define cfg_loader_bank0_end     (LDRFLASH_NORMAL_ADDRESS + LDRFLASH_TOTAL_SIZE)
  define cfg_loader_bank1_start   (LDRFLASH_MIRROR_ADDRESS)
  define cfg_loader_bank1_end     (LDRFLASH_MIRROR_ADDRESS + LDRFLASH_TOTAL_SIZE)
  define cfg_write_protected_size (LDRFLASH_TOTAL_SIZE)

  ##################################################################################
  ## The following defines are for the flash component & relate to the unprotetcted
  ## area of flash
  ##################################################################################
  define cfg_bank0_unprotect_start (FLASH_BANK0_ADDR)
  define cfg_bank1_unprotect_start (FLASH_BANK1_ADDR)

  ##################################################################################
  ## The total size of a flash bank - Assume always the same
  ##################################################################################
  define cfg_total_flash_size  (FLASH_BANK_SIZE)

} ## End Loader_MemDefs ##

################################################################################
## Board_System_Clock_Dividers()
## Define the physical system clock dividers of the board. 
## THESE VALUES ARE SET __ONLY HERE__ and exported 
##  up to HOSTBOOT AND up to the LOADER and MAIN DRIVERS 
##

proc Board_System_Clock_Dividers {

  HALF_DIVIDE = (0x00000001)   ## used to flag the divide by say 3.5
  PHASE_1     = (0x10000000)   ## used to set the phase to #1
  PHASE_2     = (0x20000000)   ## used to set the phase to #2  else default 0 used

## to use half divider follow example as below
##  VID_MEM_CLOCK_DIVIDER   = ( ( 4 *2) |HALF_DIVIDE |PHASE_1 )


                            ## all xxx_CLOCK_DIVIDER are x2 and the bottom bit used for 1/2
  C200_CORE_CLOCK_DIVIDER = ( ( 3 *2)	        ) ## NOT FROM DATA SHEET, DIRECTLY FROM ST
  STBUS_CLOCK_DIVIDER     = ( ( 6 *2)	        )
  COMMS_CLOCK_DIVIDER     = ( (10 *2) 	        )
  HDDI_CLOCK_DIVIDER      = ( ( 6 *2)	        )

  VID_MEM_CLOCK_DIVIDER   = ( ( 5 *2)           )
  VID_CLK2_CLOCK_DIVIDER  = ( (10 *2)	        )
  VID_CLK3_CLOCK_DIVIDER  = ( (20 *2)	        )
  AUD_DSP_CLOCK_DIVIDER   = ( (10 *2)	        )

  EMI_CLOCK_DIVIDER       = ( ( 6 *2)	        )
  EMI_MPX_CLOCK_DIVIDER   = ( (16 *2)	       	)
  EMI_FLASH_CLOCK_DIVIDER = ( (14 *2)	        )
  EMI_SDRAM_CLOCK_DIVIDER = ( ( 6 *2) 	        )
}

################################################################################
## Board_System_Clock_Frequencies()
## Define the physical system clock frequencies of the board. 
## THESE VALUES ARE SET __ONLY HERE__ and exported 
##  up to HOSTBOOT AND up to the LOADER and MAIN DRIVERS 
##	for 500MHz

proc Board_System_Clock_Frequencies {
  SYSTEM_CLOCK_SOURCE_FREQ = 27000000  ## 27MHz
  MAIN_PLL_DIVIDE_M_VALUE  = 24  ## 18  for 600MHz
  MAIN_PLL_DIVIDE_N_VALUE  = 240 ## 200 for 600MHz
  MAIN_PLL_DIVIDE_P_VALUE  = 0

  ## this top value needs deriving
  MAIN_PLL_FREQUENCY       = (((SYSTEM_CLOCK_SOURCE_FREQ*2)/MAIN_PLL_DIVIDE_M_VALUE)*MAIN_PLL_DIVIDE_N_VALUE )/(1<<MAIN_PLL_DIVIDE_P_VALUE)
  PLL_FS_FREQUENCY         = MAIN_PLL_FREQUENCY  
  PLL_CS_FREQUENCY         = MAIN_PLL_FREQUENCY	

  write Main PLL Frequency setting is -d (MAIN_PLL_FREQUENCY)

}

################################################################################
## Board_System_Clock_Configs()
## This procedure will be used by the loader/main drivers
## since they want the frequencies rather than the divide values

proc Board_System_Clock_Configs {

  Board_System_Clock_Dividers
  Board_System_Clock_Frequencies

  define  boot_cfg_main_pll_frequency        (MAIN_PLL_FREQUENCY)
  define  boot_cfg_pll_fs_frequency          (PLL_FS_FREQUENCY)
  define  boot_cfg_pll_cs_frequency          (PLL_CS_FREQUENCY)

                            ## all xxx_CLOCK_DIVIDER are x2 and the bottom bit used for 1/2
  define  boot_cfg_c200_core_clock_frequency (MAIN_PLL_FREQUENCY*2/(C200_CORE_CLOCK_DIVIDER & 0xFFFF) )
  write "C200 CORE FREQUENCY = " -d          (MAIN_PLL_FREQUENCY*2/(C200_CORE_CLOCK_DIVIDER & 0xFFFF) )
  define  boot_cfg_stbus_clock_frequency     (MAIN_PLL_FREQUENCY*2/(STBUS_CLOCK_DIVIDER     & 0xFFFF) )
  define  boot_cfg_comms_clock_frequency     (MAIN_PLL_FREQUENCY*2/(COMMS_CLOCK_DIVIDER     & 0xFFFF) )
  define  boot_cfg_hddi_clock_frequency      (MAIN_PLL_FREQUENCY*2/(HDDI_CLOCK_DIVIDER      & 0xFFFF) )
											  
  define  boot_cfg_vid_mem_clock_frequency   (MAIN_PLL_FREQUENCY*2/(VID_MEM_CLOCK_DIVIDER   & 0xFFFF) )
  write "SMI FREQUENCY = " -d                (MAIN_PLL_FREQUENCY*2/(VID_MEM_CLOCK_DIVIDER   & 0xFFFF) )
  define  boot_cfg_clk2_clock_frequency      (MAIN_PLL_FREQUENCY*2/(VID_CLK2_CLOCK_DIVIDER  & 0xFFFF) )
  define  boot_cfg_clk3_clock_frequency      (MAIN_PLL_FREQUENCY*2/(VID_CLK3_CLOCK_DIVIDER  & 0xFFFF) )
  define  boot_cfg_dsp_clock_frequency       (MAIN_PLL_FREQUENCY*2/(AUD_DSP_CLOCK_DIVIDER   & 0xFFFF) )
											  
  define  boot_cfg_emi_clock_frequency       (MAIN_PLL_FREQUENCY*2/(EMI_CLOCK_DIVIDER       & 0xFFFF) )
  define  boot_cfg_mpx_clock_frequency       (MAIN_PLL_FREQUENCY*2/(EMI_MPX_CLOCK_DIVIDER   & 0xFFFF) )
  define  boot_cfg_flash_clock_frequency     (MAIN_PLL_FREQUENCY*2/(EMI_FLASH_CLOCK_DIVIDER & 0xFFFF) )
  define  boot_cfg_sdram_clock_frequency     (MAIN_PLL_FREQUENCY*2/(EMI_SDRAM_CLOCK_DIVIDER & 0xFFFF) )
}

################################################################################
## Board_System_Host_Boot_Clock_Configs()
## This procedure will be used by the hostboot/romboot
## since they want the divider values rather than the frequencies

proc Board_System_Host_Boot_Clock_Configs {

                            ## all xxx_CLOCK_DIVIDER are x2 and the bottom bit used for 1/2
  Board_System_Clock_Dividers
  Board_System_Clock_Frequencies

  define  boot_cfg_main_pll_frequency    (MAIN_PLL_FREQUENCY)
##  define  boot_cfg_pll_fs_frequency      (PLL_FS_FREQUENCY)
##  define  boot_cfg_pll_cs_frequency      (PLL_CS_FREQUENCY)

  define  boot_cfg_main_PLL_divider_M      (MAIN_PLL_DIVIDE_M_VALUE)
  define  boot_cfg_main_PLL_divider_N      (MAIN_PLL_DIVIDE_N_VALUE)
  define  boot_cfg_main_PLL_divider_P      (MAIN_PLL_DIVIDE_P_VALUE)

  define  boot_cfg_c200_core_clock_divider_x2 (C200_CORE_CLOCK_DIVIDER)
  write "C200 CORE FREQUENCY = " -d           (MAIN_PLL_FREQUENCY*2/(C200_CORE_CLOCK_DIVIDER & 0xFFFF) )
  define  boot_cfg_stbus_clock_divider_x2     (STBUS_CLOCK_DIVIDER)
  define  boot_cfg_comms_clock_divider_x2     (COMMS_CLOCK_DIVIDER)
  define  boot_cfg_hddi_clock_divider_x2      (HDDI_CLOCK_DIVIDER)

  define  boot_cfg_vid_mem_clock_divider_x2   (VID_MEM_CLOCK_DIVIDER)
  define  boot_cfg_vid_mem_clock_frequency    (MAIN_PLL_FREQUENCY*2/(VID_MEM_CLOCK_DIVIDER & 0xFFFF) )
  write "SMI FREQUENCY = " -d                 (MAIN_PLL_FREQUENCY*2/(VID_MEM_CLOCK_DIVIDER & 0xFFFF) )
  define  boot_cfg_clk2_clock_divider_x2      (VID_CLK2_CLOCK_DIVIDER)
  define  boot_cfg_clk3_clock_divider_x2      (VID_CLK3_CLOCK_DIVIDER)
  define  boot_cfg_dsp_clock_divider_x2       (AUD_DSP_CLOCK_DIVIDER)

  define  boot_cfg_emi_clock_divider_x2       (EMI_CLOCK_DIVIDER)
  define  boot_cfg_mpx_clock_divider_x2       (EMI_MPX_CLOCK_DIVIDER)
  define  boot_cfg_flash_clock_divider_x2     (EMI_FLASH_CLOCK_DIVIDER)
  define  boot_cfg_sdram_clock_divider_x2     (EMI_SDRAM_CLOCK_DIVIDER)

}

###############################################################################
############## MEDIUM LEVEL PROCEDURES ########################################
###############################################################################

################################################################################
## Board()
## Define the physical memory map of the board. Medium level cfg procedure
##    called by   Board_MemoryMap() 
##     and        Board_MemoryMap_WithLoader() 

proc Board {

  chip STi5514

##  write Flash non romboot size = -d (FLASH_NORMAL_SIZE)
##  write Flash RESERVED size    = -d (RESERVED_FLASH_SIZE)
##  write Flash CONFIG addr      = -x (CONFIG_ADDR)
##  write Flash CONFIG size      = -d (CONFIG_SIZE)

  #################
  ## memory regions