pxa255.dat

wince的boot程序下载：并口JFlashmm源代码。 VC6.0编译。如果用新的flash芯片需要修改源代码后编译。

handled, and at least one must be the main processor. Specify that a 
device is present with the string 'Enabled' or not present with the string 
'Disabled'. Each device that is enabled requires a specification for the 
number of bits in the JTAG instruction register.  The controlling entity,
usually the main processor is identified by the string 'Controller'.
The order of the components is from TDI to TDO. The procedure needs to 
know if the device is the last 
**************************************************************************** 
*/
/* TDI --------> */  Enabled    5   Controller  Last
                     Disabled   0   Other       More
                     Disabled   0   Other       More
                     Disabled   0   Other       More
                     Disabled   0   Other       More    /* TDO ---------> */
/*
****************************************************************************
Additional flash component UNLOCK controls: 4 addition pins can be defined 
that would be controlled to UNLOCK a flash memory device that has external 
locking pins. Any unused pins should be set to 9999. Specify the signal level
required to UNLOCK the flash. These signals will be reversed to re-lock the 
flash after programming. 
**************************************************************************** 
*/
    9999    1   /* N/A */
    9999    1   /* N/A */
    9999    1   /* N/A */
    9999    1   /* N/A */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 3 - DO NOT MODIFY THIS DATA
**************************************************************************** 
*/
    3333
/*
****************************************************************************
number of flash devices in parallel on the bus
**************************************************************************** 
*/
	2  
/*
****************************************************************************
position of nsdcas signal - toggled in parallel with any chip select
**************************************************************************** 
*/
	242		/* nsdcas */
/*
****************************************************************************
Flash programming Mode: WORD or BUFFER
WORD programming is useful for doing things like smoothly crossing device 
boundaries but is a little slower. 
**************************************************************************** 
*/
	BUFFER		/* WORD or BUFFER is the allowed entry */

/*
****************************************************************************
E N D   O F   D A T A 
**************************************************************************** 
*/
/*
-------------------------------------------------------------------------
-- DATE & TIME    :  Thu May  2 13:02:24 2002
-- File Type      :  BSDL Description for Top-Level Entity pxa250_jtag_C0
-- Revision       :  C0 v1_4
-- Author         :  jboyer
-------------------------------------------------------------------------

entity pxa250_jtag_C0 is

generic(PHYSICAL_PIN_MAP : string := "MBGA_256"); 

port(
    boot_sel     : in      bit_vector(2 downto 0);
    gpio         : inout   bit_vector(89 downto 0);
    dqm_0        : out     bit;
    dqm_1        : out     bit;
    dqm_2        : out     bit;
    dqm_3        : out     bit;
    ma           : out     bit_vector(25 downto 0);
    md           : inout   bit_vector(31 downto 0);
    ncs_0        : out     bit;
    noe          : out     bit;
    nsdcas       : out     bit;
    nsdcs_0      : out     bit;
    nsdcs_1      : buffer  bit;
    nsdras       : out     bit;
    nwe          : out     bit;
    sdcke        : buffer  bit_vector(1 downto 0);
    sdclk_0      : buffer  bit;
    sdclk_1      : out     bit;
    sdclk_2      : buffer  bit;
    mmcmd        : inout   bit;
    mmdat        : inout   bit;
    nbatt_fault  : in      bit;
    nreset       : in      bit;
    nreset_out   : buffer  bit;
    nvdd_fault   : in      bit;
    pextal       : linkage bit;
    pwr_en       : buffer  bit;
    pxtal        : linkage bit;
    test         : in      bit;
    testclk      : in      bit;
    textal       : linkage bit;
    scl          : inout   bit;
    sda          : inout   bit;
    txtal        : linkage bit;
    usb_n        : inout   bit;
    usb_p        : inout   bit;
    tdi          : in      bit;
    tms          : in      bit;
    tck          : in      bit;
    tdo          : out     bit;
    ntrst        : in      bit;
    vdd          : linkage bit_vector(8 downto 0);
    vss          : linkage bit_vector(5 downto 0);
    vddn         : linkage bit_vector(13 downto 0);
    vssn         : linkage bit_vector(14 downto 0);
    pll_vcc      : linkage bit;
    pll_sense    : linkage bit;
    vcckp        : linkage bit;
    batt_vcc     : linkage bit;
    vddq         : linkage bit_vector(5 downto 0);
    vssq         : linkage bit_vector(12 downto 0)
    );

use STD_1149_1_1994.all; -- Get IEEE 1149.1-1994 attributes and definitions 

attribute COMPONENT_CONFORMANCE of pxa250_jtag_C0:entity is "STD_1149_1_1993";

attribute PIN_MAP of pxa250_jtag_C0 : entity is PHYSICAL_PIN_MAP; 
constant MBGA_256 : PIN_MAP_STRING :=
   "gpio       :(D10,D3,F2,G3,F15,D16,E15,E16,F16,R13," &
                 "T9,P9,A8,B8,D8,E8,B3,C3,A2,A3," &
                 "A4,D5,A5,C5,A6,E5,D6,E6,B7,C7," &
                 "D7,E7,M16,N16,M13,P16,R16,P14,R15,T15," &
                 "T14,P13,C15,B15,B14,A15,D13,B13,F8,F10," &
                 "E13,B10,B11,A12,A14,A13,T13,A16,E11,A10," &
                 "E10,C9,B9,A9,D9,E9,F9,M12,N15,N12," &
                 "N14,C1,D12,E12,T8,B4,B5,B6,A7,F7," &
                 "F12,F14,G15,H14,J11,J12,K14,L13,L12,L10)," &
   "scl        :D11," &
   "sda        :A11," &
   "usb_n      :B12," &
   "usb_p      :C12," &
   "mmdat      :B16," &
   "mmcmd      :D14," &
   "md         :(P12,R11," &
                 "P10,L8,P8,P7,R7,P6,T3,N1,M2,L4," &
                 "K3,J4,H5,H3,M10,T12,N10,P11,T11,R9," &
                 "T10,M9,M7,M6,T7,N6,T6,L5,M5,N4)," &
   "pwr_en     :L11," &
   "nreset_out :K11," &
   "sdclk_0    :D2," &
   "sdclk_1    :F5," &
   "sdclk_2    :D1," &
   "sdcke      :(E3,E4)," &
   "nsdcs_0    :F1," &
   "nsdcs_1    :G6," &
   "dqm_0      :M8," &
   "dqm_1      :B1," &
   "dqm_2      :B2," &
   "dqm_3      :L7," &
   "nsdcas     :F3," &
   "nsdras     :E1," &
   "nwe        :G4," &
   "noe        :G5," &
   "ncs_0      :N8," &
   "ma         :(P4,T5,P5,R5,T4,R3," &
                 "P2,R1,P1,N3,M3,M1,L3,L1,K6,K5," &
                 "K2,K1,J1,J3,J5,J6,H6,H1,H2,G1)," &
   "test       :G12," &
   "testclk    :G11," &
   "nvdd_fault :K13," &
   "nbatt_fault:K12," &
   "boot_sel   :(F13,G13,G16)," &
   "nreset     :J13," &
   "pextal     :K16," &
   "textal     :L15," &
   "pxtal      :K15," &
   "txtal      :L16," &
   "tms        :H13," &
   "tck        :H12," &
   "tdi        :H15," &
   "tdo        :H16," &
   "ntrst      :H11," &
   "vdd        :(L9,L6,K10,K8,J7,H10,G9,G7,F11)," &
   "vss        :(T1,J9,J8,H9,H8,C16)," &
   "vddn       :(D4,A1,F4,H4," &
                 "M14,K4,N11,N13,N7,N9,N5,P3,M4,T16)," &
   "vssn       :(C2,E2,G2,J2,L2,N2,R2,P15,M15," &
                 "R14,R12,R10,R8,R6,R4)," &
   "pll_vcc    :J15," &
   "pll_sense  :J16," &
   "vcckp      :T2," &
   "batt_vcc   :M11," &
   "vddq       :(C10,G14,E14,C13,C6,D15)," &
   "vssq       :(C14,C11,C8," &
                 "C4,G8,F6,G10,K7,H7,J14,J10,L14,K9)";

attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (40.0e6, BOTH);
attribute TAP_SCAN_RESET of ntrst : signal is true;

attribute INSTRUCTION_LENGTH of pxa250_jtag_C0 : entity is 5;
attribute INSTRUCTION_OPCODE of pxa250_jtag_C0 : entity is
   "extest (00000),"  &
   "bypass (11111),"  &
   "sample (00001),"  &
   "idcode (11110),"  &
   "clamp (00100),"  &
   "highz (01000)";

attribute INSTRUCTION_CAPTURE of pxa250_jtag_C0 : entity is "00001";
attribute IDCODE_REGISTER of pxa250_jtag_C0 : entity is
   "0100"  &                -- Version Number
   "1001001001100100"  &    -- Part Number
   "00000001001"  &         -- Manufacturer ID
   "1";                     -- Required by IEEE Std. 1149.1-1990

attribute REGISTER_ACCESS of pxa250_jtag_C0 : entity is
   "BOUNDARY (extest, sample), " &
   "DEVICE_ID (idcode), " &
   "BYPASS (bypass, clamp, highz)";

attribute BOUNDARY_LENGTH of pxa250_jtag_C0 : entity is 410;
attribute BOUNDARY_REGISTER of pxa250_jtag_C0 : entity is
-- num     cell          port   function safe  [ccell  disval  rslt]
   "0    ( bc_1,            *,   control,   0)," &
   "1    ( bc_1,            *,   control,   0)," &