pxa255.dat

wince的boot程序下载：并口JFlashmm源代码。 VC6.0编译。如果用新的flash芯片需要修改源代码后编译。

/* dbpxa255.dat version 1.0
****************************************************************************

    This data file contains the JTAG and board configuration data required 
    for multi-mode JFlash. This data file is a text file with specific 
    format requirements.

    Comment blocks can be defined using the old-style C comment blocks. 
    The difference is that the delimiter characters must have whitespace 
    on both sides. 

    Data may be string data, or numeric. String data is only allowed 
    at specific positions within this file. Numeric data can be decimal, 
    hexadecimal, or octal. 
    Decimal data is assumed, and HEX data may be denoted by a 
    preceding 'X' character.

    Valid HEX data:
        xA0000000
        XA4090000
        Xff

    Valid OCTAL data:
        o765
        O123545

    The data required to fill in this table comes from knowledge of the 
    BSDL file for the processor, the development board user's guide, 
    and specifications for the flash components. 

    Data is position dependent in terms of order. Whitespace is the 
    delimiter for the data and may be used as necessary to keep the 
    data in reasonably readable format. 

    There are checkpoints within this file that are used as validation 
    that the data alignment is correct. DO NOT MODIFY THE CHECKPOINT DATA. 

    The filename of this file is used as the parameter for JFlash.
*/ 

/*
****************************************************************************
File Identification strings to display from JFlash  
**************************************************************************** 
*/
    DBPXA255    /* Position 0 - Supported Processor Code Name or Number */
    Lubbock     /* Supported Development platform name or number */
    1.0         /* Version number of this data file */
    VL00000001  /* Version lock code for compatibility to JTAG engine */

/*
****************************************************************************
Basic JTAG setup required by JFlash
**************************************************************************** 
*/
    410     /* The number of bits in the Boundary Scan chain */
    5       /* The number of bits in the instruction register */
    X0      /* EXTEST instruction in HEX */
    X1E     /* IDCODE instruction in HEX */
    X1F     /* BYPASS instruction */
/*
****************************************************************************
Chip select offsets: 6 total, beginning with chip select 0 and in order.
**************************************************************************** 
*/
    246  110 173 174 175 128
/*
****************************************************************************
Control Bits required for bus transactions
**************************************************************************** 
*/
    245      /* Output enable: nOE_OUT */
    244      /* Write Enable: nWE_OUT */
    93       /* Memory data upper bit control: mdupper_ctrl */
    94       /* Memory data lower bit control: mdlower_ctrl */
    183      /* Read/Write direction: RD_nWR_OUT */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 1 - DO NOT MODIFY THIS DATA
**************************************************************************** 
*/
    1111    /* position 20 */
/*
****************************************************************************
Address bit offsets beginning with A0
**************************************************************************** 
*/
    247 248 249 250 251 252 253 254     /* A0 - A7 */   
    255 256 257 258 259 260 261 262     /* A8 - A15 */
    263 264 265 266 267 268 269 270     /* A16 - A23 */
    271 272                             /* A24, A25 */
/*
****************************************************************************
Input data bit offsets beginning with D0
**************************************************************************** 
*/
    369 370 371 372 373 374 375 376     /* D0 -  D7  */
    377 378 379 380 381 382 383 384     /* D8 -  D15 */
    385 386 387 388 389 390 391 392     /* D16 - D23 */
    393 394 395 396 397 398 399 400     /* D24 - D31 */
/*
****************************************************************************
Output data bit offsets beginning with D0
**************************************************************************** 
*/
    191 192 193	194	195	196	197	198     /* D0 -  D7  */
    199 200	201	202	203 204 205 206     /* D8 -  D15 */
    207 208 209 210 211 212 213 214     /* D16 - D23 */
    215 216 217 218 219 220 221 222     /* D24 - D31 */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 2 - DO NOT MODIFY THIS DATA
**************************************************************************** 
*/
    2222    /* position 111 */
/*
****************************************************************************
Width of data bus. Only 16 or 32 are allowed as values 
**************************************************************************** 
*/
    32
/*
****************************************************************************
Memory Space Definition for chip selects. The memory addresses are defined 
by a lower and upper limit and the chip select that is used to access this
address. The chip selects are identified by an integer.
Only 6 regions are allowed. If there are fewer regions on the platform, 
then specify the unused regions with XFFFFFFFF as the lower and upper 
region limits and specify the highest chip select for these regions.  
**************************************************************************** 
*/
/*  Lower Address       Upper Address       Chip Select */
    X00000000           X02000000           0
    X04000000           X06000000           1
    X08000000           X08000100           2
    X0C000000           X10000000           3
    X10000000           X10400000           4
    X14000000           X18000000           5
/*
****************************************************************************
Processor JTAG ID string. The upper 4 bits that define the stepping are not
required here, but must be defined afterward to equate the value to the 
named stepping. 
**************************************************************************** 
*/
    1001001001100100    /* Processor ID */ 
    00000001001         /* Intel Manufacturer Code */
    1                   /* required by JTAG Standards */
/*
****************************************************************************
Stepping labels relative to the top 4 bits of the chip ID. 
16 values required. 
**************************************************************************** 
*/
    ??       /* id = 0 , data position 131 */
    ??       /* id = 1 */
    ??       /* id = 2 */
    ??       /* id = 3 */
    ??       /* id = 4 */
    ??       /* id = 5 */
    A0       /* id = 6 */
    ??       /* id = 7 */
    ??       /* id = 8 */
    ??       /* id = 9 */
    ??       /* id = 10 */
    ??       /* id = 11 */
    ??       /* id = 12 */
    ??       /* id = 13 */
    ??       /* id = 14 */
    ??       /* id = 15 */
/*
****************************************************************************
Default High bits. These are pins on the chain that are required to be set 
high by default. This list contains some usual pins, and allows for 20 
arbitrary additional pins to be set. This list as with all lists is required 
to have a fixed number of entries. All entries that are not used should be 
set to 9999 
**************************************************************************** 
*/
    /* Normally high */

    246     /* nCS0_OUT */
    110     /* nCS1_OUT */      15      /* nCS1 control pin */
    173     /* nCS2_OUT */      78      /* nCS2 control pin */
    174     /* nCS3_OUT */      79      /* nCS3 control pin */
    175     /* nCS4_OUT */      80      /* nCS4 control pin */
    128     /* nCS5_OUT */      33      /* nCS5 control pin */
    9999    /* SPARE    */
    244     /* nWE_OUT */
    245     /* nOE_OUT */
    223     /* dqm2_3_ctrl - address lines enable */
    226     /* dqm0_1_ctrl - DQM Control */
    94      /* mdlower_ctrl - memory data lower 16 bits */
    93      /* mdupper_ctrl - memory data upper 16 bits */
    225     /* nwe_ctrl */
    182     /* nsdcs_3  */
    181     /* nsdcs_2  */
    234     /* nsdcs_0  */
    235     /* nsdcs_1  */
    243     /* nsdras */
    227     /* pwr_en        */
    405     /* nbatt_fault */
    404     /* nvdd_fault */

    /* Arbitrary Additional Pins */

    147    /* GPIO 52 */
    52     /* GPIO 52 Control */
    148    /* GPIO 53 */
    53     /* GPIO 53 Control */
    86      /* GPIO 86 Control */
    87      /* GPIO 87 Control */
    88      /* GPIO 88 Control */
    224     /* ncs_0 control */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
/*
****************************************************************************
JTAG Chain description: This section defines the position of components 
on the chain so that these components can be accounted for and bypassed
during the programming operation. There are up to 5 devices that can be