📄 etherdev.h
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#ifndef __ETHERDEV_H__
#define __ETHERDEV_H__
#include "uip.h"
#include "bsp.h"
#include "config.h"
#define ETH_REG_BASE 0x83400000 // Hardwired to 0x0300
typedef unsigned char uint8;
typedef unsigned short uint16;
typedef unsigned int uint32;
// Registers common to all pages.
#define CR ETH_REG_BASE + 0x00 // Control register
// Control register bits
#define PS1 0x80 // Page select bit 1
#define PS0 0x40 // Page select bit 0
#define RD2 0x20 // Remote DMA control bit 2
#define RD1 0x10 // Remote DMA control bit 1
#define RD0 0x08 // Remote DMA control bit 0
#define TXP 0x04 // Transmit packet bit
#define STA 0x02 // Start bit (a flag only)
#define STP 0x01 // Stop bit transceiver ctrl
#define RDMA 0x10 // Remote DMA port
#define RESET 0x18 // Reset port
// Page 0 read/write registers.
#define BNRY ETH_REG_BASE + 0x03 // Boundary register
#define ISR ETH_REG_BASE + 0x07 // Interrupt status register
// Interrupt status register bits
#define RST 0x80 // Reset state indicator bit
#define RDC 0x40 // Remote DMA complete bit
#define CNT 0x20 // Network tally counter MSB set
#define OVW 0x10 // Receive buffer exhausted
#define TXE 0x08 // Transmit abort error bit
#define RXE 0x04 // Receive error report bit
#define PTX 0x02 // Successful packet transmit
#define PRX 0x01 // Successful packet receive
// Page 0 read only registers.
#define CLDA0 ETH_REG_BASE + 0x01
#define CLDA1 ETH_REG_BASE + 0x02
#define TSR ETH_REG_BASE + 0x04
#define NCR ETH_REG_BASE + 0x05
#define FIFO ETH_REG_BASE + 0x06
#define CRDA0 ETH_REG_BASE + 0x08
#define CRDA1 ETH_REG_BASE + 0x09
#define _8019ID0 ETH_REG_BASE + 0x0A
#define _8019ID1 ETH_REG_BASE + 0x0B
#define RSR ETH_REG_BASE + 0x0C
#define CNTR0 ETH_REG_BASE + 0x0D
#define CNTR1 ETH_REG_BASE + 0x0E
#define CNTR2 ETH_REG_BASE + 0x0F
// Page 0 write only registers.
#define PSTART ETH_REG_BASE + 0x01 // Receive page start register
#define PSTOP ETH_REG_BASE + 0x02 // Receive page stop register
#define TPSR ETH_REG_BASE + 0x04 // Transmit page start register
#define TBCR0 ETH_REG_BASE + 0x05 // Transmit byte count register 0
#define TBCR1 ETH_REG_BASE + 0x06 // Transmit byte count register 1
#define RSAR0 ETH_REG_BASE + 0x08 // Remote start address register 0
#define RSAR1 ETH_REG_BASE + 0x09 // Remote start address register 0
#define RBCR0 ETH_REG_BASE + 0x0A // Remote byte count register 0
#define RBCR1 ETH_REG_BASE + 0x0B // Remote byte count register 1
#define RCR ETH_REG_BASE + 0x0C // Receive configuration register
// Receive configuration register bits (write in page 0, read in page 2)
#define MON 0x20 // Monitor mode select bit
#define PRO 0x10 // Promiscuous mode select bit
#define AM 0x08 // Multicast packet accept bit
#define AB 0x04 // Broadcast packet accept bit
#define AR 0x02 // Runt packet accept bit
#define SEP 0x01 // Error packet accept bit
#define TCR ETH_REG_BASE + 0x0D // Transmit configuration register
// Transmit configuration register bits
#define OFST 0x10 // Collision offset enable bit
#define ATD 0x08 // Auto transmit disable select bit
#define LB1 0x04 // Loopback mode select bit 1
#define LB0 0x02 // Loopback mode select bit 0
#define CRC 0x01 // CRC generation inhibit bit
#define DCR ETH_REG_BASE + 0x0E // Data configuration register
// Data configuration register bits (write in page 0, read in page 2)
#define FT1 0x40 // FIFO threshold select bit 1
#define FT0 0x20 // FIFO threshold select bit 0
#define ARM 0x10 // Auto-initialise remote
#define LS 0x08 // Loopback select bit
#define LAS 0x04 // Set to 0 (pwrup = 1)
#define BOS 0x02 // Byte order select bit
#define WTS 0x01 // Word transfer select bit
#define IMR ETH_REG_BASE + 0x0F // Interrupt mask register
// Interrupt mask register bits
// Each enable bit correspons with an interrupt flag in ISR
// Page 1 read/write registers.
#define PAR0 ETH_REG_BASE + 0x01 // Physical address register 0
#define PAR1 ETH_REG_BASE + 0x02 // Physical address register 1
#define PAR2 ETH_REG_BASE + 0x03 // Physical address register 2
#define PAR3 ETH_REG_BASE + 0x04 // Physical address register 3
#define PAR4 ETH_REG_BASE + 0x05 // Physical address register 4
#define PAR5 ETH_REG_BASE + 0x06 // Physical address register 5
#define CURR ETH_REG_BASE + 0x07 // Current receive buffer page
#define MAR0 ETH_REG_BASE + 0x08
#define MAR1 ETH_REG_BASE + 0x09
#define MAR2 ETH_REG_BASE + 0x0A
#define MAR3 ETH_REG_BASE + 0x0B
#define MAR4 ETH_REG_BASE + 0x0C
#define MAR5 ETH_REG_BASE + 0x0D
#define MAR6 ETH_REG_BASE + 0x0E
#define MAR7 ETH_REG_BASE + 0x0F
// Page 2 read only registers.
// Each previously defined in page 0 write only.
//#define PSTART ETH_REG_BASE + 0x01
//#define PSTOP ETH_REG_BASE + 0x02
//#define TPSR ETH_REG_BASE + 0x04
//#define RCR ETH_REG_BASE + 0x0C
//#define TCR ETH_REG_BASE + 0x0D
//#define DCR ETH_REG_BASE + 0x0E
//#define IMR ETH_REG_BASE + 0x0F
// Page 3 read/write registers.
#define _9346CR ETH_REG_BASE + 0x01 // 9346 EEPROM command register
// 9346 EEPROM command register bits
#define EEM1 0x80 // RTL8019AS operating mode bit 1
#define EEM0 0x40 // RTL8019AS operating mode bit 0
#define EECS 0x08 // 9346 EEPROM chip select bit
#define EESK 0x04 // 9346 EEPROM serial clock bit
#define EEDI 0x02 // 9346 EEPROM data input bit
#define EEDO 0x01 // 9346 EEPROM data output bit
#define BPAGE ETH_REG_BASE + 0x02
#define CONFIG1 ETH_REG_BASE + 0x04 // RTL9019AS config register 1
// RTL9019AS config register 1 bits
#define IRQEN 0x80 // IRQ enable bit (WR protected)
#define IRQS2 0x40 // IRQ line select bit 2
#define IRQS1 0x20 // IRQ line select bit 1
#define IRQS0 0x10 // IRQ line select bit 0
#define IOS3 0x08 // I/O base address select bit 3
#define IOS2 0x04 // I/O base address select bit 2
#define IOS1 0x02 // I/O base address select bit 1
#define IOS0 0x01 // I/O base address select bit 0
#define CONFIG2 ETH_REG_BASE + 0x05 //
// RTL9019AS config register 2 bits
#define PL1 0x80 // Network medium type select bit 1
#define PL0 0x40 // Network medium type select bit 0
#define BSELB 0x20 // Boot ROM disable (WR protected)
#define BS4 0x10 // Boot ROM configuration bit 4
#define BS3 0x08 // Boot ROM configuration bit 3
#define BS2 0x04 // Boot ROM configuration bit 2
#define BS1 0x02 // Boot ROM configuration bit 1
#define BS0 0x01 // Boot ROM configuration bit 0
#define CONFIG3 ETH_REG_BASE + 0x06 // RTL9019AS config register 3
// RTL9019AS config register 3 bits
#define PNP 0x80 // Plug & play mode indicator bit
#define FUDUP 0x40 // Full duplex mode select bit
#define LEDS1 0x20 // LED output select bit 1
#define LEDS0 0x10 // LED output select bit 0
#define SLEEP 0x04 // Sleep mode select bit
#define PWRDN 0x02 // Power down mode select bit
#define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg
// Page 3 read only registers.
#define CONFIG0 ETH_REG_BASE + 0x03 // RTL9019AS config register 0
// RTL9019AS config register 0 bits
#define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)
#define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)
#define AUI 0x20 // AUI input pin state bit
#define PNPJP 0x10 // PNP jumper pin state bit
#define JP 0x08 // JP input pin state bit
#define BNC 0x04 // Thinnet mode indication bit
#define CSNSAV ETH_REG_BASE + 0x08
#define INTR ETH_REG_BASE + 0x0B
#define CONFIG4 ETH_REG_BASE + 0x0D
// Page 3 write only registers.
#define TEST ETH_REG_BASE + 0x07
#define HLTCLK ETH_REG_BASE + 0x09
#define FMWP ETH_REG_BASE + 0x0C
/* 赏屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯?
? Public Function Prototypes ?
韧屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯屯? */
int etherdev_init(void);
void etherdev_send(void);
unsigned int etherdev_read(void);
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