rominit.s

This file contains board-specific information for the Motorola LoPEC in support of the lopec BSP. S

*/

FUNC_BEGIN(mpc107RegMod)

	xor	r0,r0,r0		/* clear r0 */

	/* load register addresses to device-register, PCI_CAR, and PCI_CDR */

	addis	r7,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r7,r7,LO(CNFG_PCI_HOST_BRDG)
	add	r7,r7,r3		/* add register offset */
	addis	r8,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r8,r8,LO(PCI_MSTR_PRIMARY_CAR)
	addis	r9,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r9,r9,LO(PCI_MSTR_PRIMARY_CDR)

	/* adjust the addresses to CDR and device-register */

	andi.	r12,r3,0x3		/* mask register offset */
	add	r9,r9,r12		/* adjust it */
	addi	r12,r0,0x3		/* load mask (lower 2-bits) */
	andc	r7,r7,r12		/* mask of lower 2-bits */

	/* write register value to CAR */

	stwbrx	r7,r0,r8		/* write register value to CAR */
	sync				/* ensure memory access is complete */

	/* determine the size of the data operation */

	cmpli	0,0,r4,0x04		/* is this a word i/o operation? */
	bc	0x0c,0x02,andor32	/* branch to word i/o code */
	cmpli	0,0,r4,0x02		/* is this a half-word i/o operation? */
	bc	0x0c,0x02,andor16	/* branch to half-word i/o code */
	cmpli	0,0,r4,0x01		/* is this a byte i/o operation? */
	bc	0x0c,0x02,andor8	/* branch to byte i/o code */
	bclr	0x14,0x0		/* return to caller */

	/* word size data operations */

andor32:				/* READ/MODIFY(AND/OR)/WRITE */
	lwbrx	r7,r0,r9		/* load(read) device data into r7 */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stwbrx	r7,r0,r9		/* store(write) r7 to device reg */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */

	/* half-word size data operations */

andor16:				/* READ/MODIFY(AND/OR)/WRITE */
	lhbrx	r7,r0,r9		/* load(read) device data into r7 */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	sthbrx	r7,r0,r9		/* store(write) r7 to device reg */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */

	/* byte data size operations */

andor8:					/* READ/MODIFY(AND/OR)/WRITE */
	lbz	r7,0(r9)		/* load(read) device data into r7 */
	sync				/* ensure memory access is complete */
	and	r7,r7,r5		/* reg7 &= reg5 */
	or	r7,r7,r6		/* reg7 |= reg6 */
	stb	r7,0(r9)		/* store(write) r7 to device reg */
	sync				/* ensure memory access is complete */
	bclr	0x14,0x0		/* return to caller */

FUNC_END(mpc107RegMod)


/***************************************************************************
*
* mpc107DefInit	- configure memory controller with default memory settings.
*
* This function	initializes the	mpc107 memory controller
* to bank 0, 32MB and assumes an 83.3MHz clock.
*
* registers used (and not saved):
*	r3, r4,	r5, r6,	r7, r8,	r9, r20
*
* RETURNS:
*     none
*
* NOMANUAL
*/

FUNC_BEGIN(mpc107DefInit)

	addis	r0,r0,0			/* insure r0 is zero */
	ori	r0,r0,0			/* insure r0 is zero */
	or	r22,r0,r0		/* preset to no memory available */
	mfspr	r20,LR			/* save return instruction pointer */

	bl	mpc107InitTableBasicPtr	/* branch around tables */

	/*
 	 * register data table (initialization values)
 	 *
 	 * this table places the mpc107 into a known state, other tables
 	 * exist for specific memory configurations
 	 */

mpc107InitTableBasic:
	/*
 	 *    reg 			     size  data	      mask
 	 *    === 			     ====  ====	      ====
 	 */

	.long MPC107_CFG_CACHE_LINE_SIZE,	1, 0x08,	0x08  
	.long MPC107_CFG_LATENCY_TIMER,		1, 0x80,	0x80

	.long MPC107_CFG_PCI_ARBITER_CNTL,	2, 0x0000,	0x0000

	.long MPC107_CFG_PWR_MGT_CFG_REG,	2, 0x0000,	0x0000
	.long MPC107_CFG_PWR_MGT_CFG_REG2,	1, 0xE0,	0x00
	.long MPC107_CFG_OUTPUT_DRIVER_REG,	1, 0xcf,	0x00

	.long MPC107_CFG_CLOCK_DRIVER_REG,	2, 0x0300,	0x0000
	.long MPC107_CFG_MISC_DRIVER_CNTL_REG,  1, 0x00,	0x00
	.long MPC107_CFG_EUMBBAR,		4, MPC107_EUMB_BASE, 0x00000000

	.long MPC107_CFG_MEM_STRT_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_MEM_STRT_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_STRT_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_ST_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_MEM_END_ADR_REG,	4, 0x001f0000,	0x00000000
	.long MPC107_CFG_MEM_END_UADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_END_ADR_REG,	4, 0x00000000,	0x00000000
	.long MPC107_CFG_EXT_MEM_END_UADR_REG,	4, 0x00000000,	0x00000000

	.long MPC107_CFG_MEM_BANK_ENABLE_REG,	1, 0x04,	0x00
	.long MPC107_CFG_PAGE_MODE_CTR_TIMER,	1, 0x00,	0x00

	.long MPC107_CFG_PROC_IF_CFG1,		4, 0xFF141010,	0x00000000
	.long MPC107_CFG_PROC_IF_CFG2,		4, 0x000C060C,	0x00000000

	.long MPC107_CFG_ECC_ERROR_CTR,		1, 0x00,	0x00
	.long MPC107_CFG_ECC_ERROR_TRIG,	1, 0x00,	0x00

	.long MPC107_CFG_ERROR_ENABLE1,		1, 0x00,	0x00
	.long MPC107_CFG_ERROR_DETECT1,		1, 0x00,	0x00
	.long MPC107_CFG_CPU_BUS_ERR_STAT,	1, 0x00,	0x00

	.long MPC107_CFG_ERROR_ENABLE2,		1, 0x00,	0x00
	.long MPC107_CFG_ERROR_DETECT2,		1, 0x00,	0x00
	.long MPC107_CFG_PCI_BUS_ERR_STAT,	1, 0x00,	0x00
	.long MPC107_CFG_CPU_PCI_ERR_ADR,	4, 0x0000e0fe,	0x00000000

	.long MPC107_CFG_MISC_REG1,		1, 0xc0,	0x00

	.long MPC107_CFG_MEM_CNTL_CFG_REG1,	4, 0x08e40000,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG2,	4, 0x17601868,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG3,	4, 0x07400000,	0x00000000
	.long MPC107_CFG_MEM_CNTL_CFG_REG4,	4, 0x25103230,	0x00000000

	.long -1, -1, -1, -1			/* table end marker */

mpc107InitTableBasicPtr:
	mfspr	r21,LR			/* load pointer to table */

mpc107InitBLoop:
	lwz	r3,0(r21)		/* load offset */
	lwz	r4,4(r21)		/* load size */
	lwz	r5,12(r21)		/* load mask (and-data) */
	lwz	r6,8(r21)		/* load data (or-data) */
	cmpi	0,0,r5,-1		/* table end? */
	bc	12,2,mpc107InitDone	/* if equal, yes, branch */
	bl	mpc107RegMod		/* perform register mod operation */
	addi	r21,r21,16		/* bump to next entry */
	b	mpc107InitBLoop		/* play it again sam */

mpc107InitDone:

	bl	waitRefresh

	/* Now turn on the memory controller */

	bl	memCtlrOn

	/* exit routine, return to caller (probably start.s) */

	or	r3,r22,r22		/* return memory size in bytes */
	mtspr	LR,r20			/* restore return instruction pointer */
	bclr	20,0			/* return to caller */

FUNC_END(mpc107DefInit)


/***************************************************************************
*
* memCtlrOn - Turn on memory controller (MEMGO bit)
*
* void memCtlrOn()
*
* NOMANUAL
*/

FUNC_BEGIN(memCtlrOn)

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,MPC107_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */
	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(MPC107_MCC1_MEMGO)
	ori	r3,r3,LO(MPC107_MCC1_MEMGO)
	or	r5,r5,r3		/* or in of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */
	bclr	20,0			/* return to caller */

FUNC_END(memCtlrOn)


/***************************************************************************
*
* memCtlrOff - Turn off memory controller
*
* void memCtlrOff()
*
* NOMANUAL
*/

FUNC_BEGIN(memCtlrOff)

	/* Clear MEMGO in MCCR1 */

	addis	r6,r0,HIADJ(CNFG_PCI_HOST_BRDG)
	ori	r6,r6,LO(CNFG_PCI_HOST_BRDG)
	addi	r3,r6,MPC107_CFG_MEM_CNTL_CFG_REG1 /* add MCCR1 offset */
	addis	r7,r0,HIADJ(PCI_MSTR_PRIMARY_CAR)
	ori	r7,r7,LO(PCI_MSTR_PRIMARY_CAR)
	stwbrx	r3,r0,r7		/* write address of MCCR1 to CAR */
	sync				/* ensure memory access is complete */

	addis	r4,r0,HIADJ(PCI_MSTR_PRIMARY_CDR)
	ori	r4,r4,LO(PCI_MSTR_PRIMARY_CDR)
	lwbrx	r5,r0,r4		/* read MCCR1 */
	sync				/* ensure memory access is complete */

	addis	r3,r0,HIADJ(MPC107_MCC1_MEMGO)
	ori	r3,r3,LO(MPC107_MCC1_MEMGO)
	andc	r5,r5,r3		/* and in complement of MEMGO */
	stwbrx	r5,r0,r4		/* write new value to MCCR1 */
	sync				/* ensure memory access is complete */

	bclr	20,0

FUNC_END(memCtlrOff)


/******************************************************************************
*
* waitRefresh -	delays for at least 200	microseconds.
*
* This subroutine's purpose is to delay execution for at least
* 200 micro seconds to allow a memory refresh to occur.
* The routine assumes the fastest lopec clock (100MHz).
* 100MHz = 100,000,000 Hz or clock cycles/sec
* Decrementer counts down 1 value in 4 clock cycles.
* Want to wait 200 usecs or .0002 seconds.
*
*	  100,000,000 *	.0002 =	20,000 clock cycles.
*	  20,000/4 = 5000 clocks.
*
* registers used (and not saved):
*	r3
*
* RETURNS:
*     none
*
* NOMANUAL
*/

FUNC_BEGIN(waitRefresh)

	sync				/* ensure instructions are complete */

	addi	r3,r0,MEM_REFRESH_DELAY	/* 200 us on 100MHz bus */
	mtspr	DEC,r3			/* set decrementer to r3 */
	sync				/* ensure instructions are complete */

refreshLoop:
	mfspr	r3,DEC			/* load decrementer value */

	cmpi	0,0,r3,0
	bc	12,1,refreshLoop	/* if r3 is > 0, branch */

	bclr	20,0			/* return to caller */

FUNC_END(waitRefresh)


/***************************************************************************
*
* iCacheOn - turn instruction cache on
*
* SYNOPSIS
* \ss
* void iCacheOn
*     (
*     void
*     )
* \se
*
* INCLUDE FILES: none
*
* RETURNS: N/A
*
*/

FUNC_BEGIN(_iCacheOn)
FUNC_BEGIN(iCacheOn)

	mfspr	r4, HID0
	ori	r4,r4,(_PPC_HID0_ICE+_PPC_HID0_ICFI) /* Set ICE & ICFI */
	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	isync

	/* Clear the ICFI bit */

	rlwinm	r3,r4,0,(_PPC_HID0_BIT_ICFI+1),(_PPC_HID0_BIT_ICFI-1) 
	mtspr	HID0, r3	/* using 2 consec instructions */
	isync

	bclr	0x14,0x0

FUNC_END(_iCacheOn)
FUNC_END(iCacheOn)


/***************************************************************************
*
* dCacheInval - Invalidate data cache
*
* SYNOPSIS
* \ss
* void dCacheInval
*     (
*     void
*     )
* \se
*
* INCLUDE FILES: none
*
* RETURNS: N/A
*
*/

FUNC_BEGIN(_dCacheInval)
FUNC_BEGIN(dCacheInval)
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI + DCE */
	ori	r3,r3,(_PPC_HID0_DCE | _PPC_HID0_DCFI)
	mfspr	r4,HID0		/* Modify HID0 to SET DCFI + DCE bits */
	or	r4,r4,r3
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI + DCE bits */
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0
FUNC_END(_dCacheInval)
FUNC_END(dCacheInval)


/***************************************************************************
*
* dCacheOn - turn data cache on
*
* SYNOPSIS
* \ss
* void dCacheOn
*     (
*     void
*     )
* \se
*
* INCLUDE FILES: none
*
* RETURNS: N/A
*
*/

FUNC_BEGIN(_dCacheOn)
FUNC_BEGIN(dCacheOn)
	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	ori	r4,r4,_PPC_HID0_DCE
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0
FUNC_END(_dCacheOn)
FUNC_END(dCacheOn)


/******************************************************************************
*
* maxErrata - apply relevant errata workarounds for Max processor.
*
* RETURNS: N/A
*
* NOMANUAL
*/

FUNC_BEGIN(maxErrata)

	/* Get the MAX revision type. If 2.7 or less apply errata fix. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,7
	bc	12,5,cpuNotMax27	/* branch if greater than 7 */

	/*
	 * The following five instructions are a workaround for errata #13
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips", Errata Version 9	6/27/00.  Description: "Speculative
	 * instruction stream may cause	duplicate data cache tags".
	 */

	li	r2,0x0
	mtspr	MSSCR0,r2		/* MSSCR0 */

	lis	r2,HI(MEMSSCR1)
	ori	r2,r2,LO(MEMSSCR1)	/* MSSCR1: L1OPQ_SIZE=0x01000000 */
	mtspr	MSSCR1,r2

	/*
	 * The following five instructions are a workaround for errata #7
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips",Errata Version 9 6/27/00.	Description: "Store data
	 * lost	when store gathering is	enabled	during cache ops".
	 */

	mfspr	r2,HID0
	lis	r3,HI(SGE_CLEAR)	/* SGE: clear */
	ori	r3,r3,LO(SGE_CLEAR)
	andc	r2,r2,r3
	mtspr	HID0,r2

cpuNotMax27:

	bclr	20,0

FUNC_END(maxErrata)


/******************************************************************************
*
* nitroErrata - apply relevant errata workarounds for Nitro processor.
*
* RETURNS: N/A
*
* NOMANUAL
*/

FUNC_BEGIN(nitroErrata)

	/* Get the NITRO revision type. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,(CPU_REV_NITRO+2)
	bc	12,5,notNitro		/* branch if greater than 0x1102 */

	/*
	 * The following five instructions are a workaround for errata #1
	 * as described	in "PowerPC Nitro Microprocessor Errata	List Release
	 * 1.x Chips",Errata Version 3 3/29/00.	Description: "Cache inhibited
	 * instruction fetches that hit	in L2 Direct Mapped SRAM space may
	 * cause processor hang".
	 */

	li	r2,0x0
	mtspr	MSSCR0,r2			/* MSSCR0 */

	lis	r2,HI(MEMSSCR1_NITRO)
	ori	r2,r2,LO(MEMSSCR1_NITRO)	/* MSSCR1: Nitro errata 1 */
	mtspr	MSSCR1,r2

notNitro:
	bclr	20,0

FUNC_END(nitroErrata)