rominit.s

This file contains board-specific information for the Motorola LoPEC in support of the lopec BSP. S

/* romInit.s - Motorola LoPEC ROM initialization module */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996-2002 Motorola, Inc. All Rights Reserved */
	.data
	.globl	copyright_wind_river
	.long	copyright_wind_river

/*
modification history
--------------------
01m,18mar02,mil  Merged from T2.1 to T2.2, updated directives.
01l,16oct01,cak  Modified as per Wind River code review.
01k,18jul01,cak  Fix to use data cache for memory controller initialization
                 instead of DRAM and other clean-ups.
01j,23apr01,cak  changes to support registered DIMMs
01i,23mar01,cak  fixed broken ECC code, including scrub routine
01h,20feb01,scb  initialize cache line size and latency timer of mpc107
01g,12jan01,djs  modifications to support the use of SPD
01f,18dec00,scb  Tweak to get flash boot to work
01e,08dec00,djs  allow sysMemParamConfig to be called
01d,07dec00,scb  consolidated errata into callable functions, matching sysALIb.s
01c,28nov00,scb  put in BYPASS_SPD capability
01b,14nov00,scb  merged mv5100, prpmc800 items into mv2100 to support lopec
01a,02nov00,djs  created based on 01h,20Oct99,rhk mv2100
*/

/*
DESCRIPTION
This module contains the entry code for	the VxWorks bootrom.
The entry point	romInit, is the	first code executed on power-up.
It sets	the BOOT_COLD parameter	to be passed to	the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "arch/ppc/mmu603Lib.h"

/* Special Purpose Registers */

#define HID1    1009    /* HID1 - Hardware Implementation Dependent Reg. 1 */
#define HID2    1011    /* HID2 - Hardware Implementation Dependent Reg. 2 */
#define MSSCR0  1014    /* MSSCR0 - Memory Subsystem Control Register 0 */
#define MSSCR1  1015    /* MSSCR1 - Memory Subsystem Control Register 1 */
#define LR      8       /* LR - Link Register */
#define CTR     9       /* CTR - Count Register */
#define DEC     22      /* DEC - Decrementer */

#define	MEMSSCR1		0x01000000 /* Memory SubSystem Ctrl Reg 1 */

#define CPU_TYPE_MAX		0x0C	   /* PPC MAX CPU */
#define CPU_TYPE_NITRO		0x800C	   /* PPC NITRO CPU */
#define CPU_REV_NITRO		0x1100	   /* PPC Nitro Rev 1.0 CPU */
#define	MEMSSCR1_NITRO		0x00040000 /* Nitro Mem SubSystem Ctrl Reg 1 */

#define SGE_CLEAR		0x00000080 /* SGE: clear */
#define DL1HWFLSH		0x00800000 /* L1 data cache HW flush bit 8 */
#define MEM_REFRESH_DELAY	5000	   /* 200 microsecond delay */

#define CACHE_STACK_ADRS (0x00003000)	   /* No-RAM cache initial stack top */
#define	CACHE_STACK_SIZE (0x1000)          /* No-RAM stack size, 4KB */

/* ABI stack size must be >= sizeof(struct sramConfigReg) */

#define ABI_STACK_SIZE	 0x44

	/* Exported internal functions */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */

	/* externals */

	FUNC_IMPORT(romStart)		/* system initialization routine */
	FUNC_IMPORT(sysMemParamConfig)	/* memory parameter initialization */

	.set	MCCR1,0
	.set	MCCR2,MCCR1+4
	.set	MCCR3,MCCR2+4
	.set	MCCR4,MCCR3+4

	.set	ERRENR1,MCCR4+4

	.set	MSR3_2_1_0,ERRENR1+4
	.set	MSR7_6_5_4,MSR3_2_1_0+4
	.set	MSER3_2_1_0,MSR7_6_5_4+4
	.set	MSER7_6_5_4,MSER3_2_1_0+4

	.set	MER3_2_1_0,MSER7_6_5_4+4
	.set	MER7_6_5_4,MER3_2_1_0+4
	.set	MEER3_2_1_0,MER7_6_5_4+4
	.set	MEER7_6_5_4,MEER3_2_1_0+4

	.set	MPMR,MEER7_6_5_4+4
	.set	MBER,MPMR+1

	_WRS_TEXT_SEG_START


/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* void romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*
* INCLUDE FILES: none
*
* RETURNS: This function does not return.
*
* SEE ALSO:
* Wind River,
* .I "Tornado BSP Developer's Kit for VxWorks"
*
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

        /* 
	 * The following isync instruction is a workaround for errata #2
	 * as described in "PowerPC Max Microprocessor Errata List Release
	 * 2.x Chips", Errata Version 9 6/27/00.  Description: "Incorrect
	 * value was written to the MSR after running POR ABIST.
	 */

	isync

	bl	cold

	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii	 "Copyright 1984-2002 Wind River Systems, Inc."
	.balign 4

cold:
	li	r31,BOOT_COLD
	bl	start			/* skip over next instruction */

warm:
	or	r31,r3,r3		/* startType to r31 */

start:
	/*
	 * Socketed flash-ROM is at 0xfff00000
	 * Soldered flash-ROM is at 0xff000000
	 *
	 * Execution on powerup always begins at 0xfff00100.
	 *
	 * The determination as to whether or not to continue to
	 * execute out of socketed flash-ROM or to jump to soldered
	 * flash-ROM (0xff000100) is controlled by a bit in the
	 * configuration header register which represents the setting
	 * of dip switch zero.  If the dip switch is on, we want to
	 * jump to soldered flash (0xff000100), if it is off we want to
	 * continue to execute out of socketed flash-ROM (0xfff00100).
	 * It is up to the software to read the configuration header
	 * and conditionally branch to 0xff000100.
	 * 
	 * Note that PPC bug is also in one of the banks (normally but
	 * not necessarily the socketed bank) and it has to make the
	 * same determination.  Thus the following snippet of code (up
	 * to romExecution:) is present in both the PPC bug and the
	 * vxWorks "romInit.s" module.  The algorithm is:
	 *                        ...
	 * if execution address is currently > 0xff80ffff
	 *     {
	 *     if dip switch zero is "on" 
	 *         {
	 *         goto address ff000100 (Soldered ROM)
	 *         }
	 *     }
	 *
	 * (continue here dip switch 0 is off)
	 *
	 * romExecution:
	 *                        ...
	 */
	 
	/* identify execution point as far as socketed or soldered. */

	bl	lreg			/* br below. load link reg w/ eaddr */
lreg:
	mfspr	r3,LR			/* copy current instruction address */
	rlwinm	r3,r3,16,16,31		/* r3 = ((r3 >> 16) & 0x0000FFFF)   */
	cmpli	0,0,r3,0xFF80		/* If flash address (< 0xff800000), */
	bc	12,0,romExecution	/* proceed to flash image */

	/* check bit 0 of software configuration header */

	addis	r3,r0,HIADJ(BOARD_CONFIG_HDR_REG) /* load S/W header reg */
	ori	r3,r3,LO(BOARD_CONFIG_HDR_REG)

	xor	r4,r4,r4		/* clear r4 */
	lbz	r4,0(r3)		/* read S/W readable header register */
	andi.	r4,r4,BOARD_CFG0	/* mask Socketed/Soldered bit */
	cmpli	0,0,r4,BOARD_CFG0	/* 1-Jumper out, 0-jumper in (bit 7) */
	beq	romExecution		/* if 1, socketed (ROM) execution */

	/* else switch is "on", branch to soldered flash */

	addis	r3,r0,HIADJ(FLASH_TEXT_ADRS)	/* Flash address */
	ori	r3,r3,LO(FLASH_TEXT_ADRS)
	mtspr	LR,r3
	bclr	0x14,0x0		/* branch via the link register */

romExecution:

	xor	r0,r0,r0

	/* initialize the stack pointer */

	lis	sp,HI(CACHE_STACK_ADRS)
	ori	sp,sp,LO(CACHE_STACK_ADRS)

	/*
	 * Set HID0 to a known state
	 * Enable machine check input pin (EMCP) for DRAM ECC detection
	 */

	lis	r3,HI(_PPC_HID0_EMCP) 		/* 0x80000000 */
	ori	r3,r3,LO(_PPC_HID0_EMCP)
	isync
	mtspr	HID0,r3

	xor	r3,r3,r3		/* clear R3 */

	/*   
	 * Set MPU/MSR to a known state
	 * Turn on FP
	 */

	lis	r3,HI(1<<(31-_PPC_MSR_BIT_FP))	   /* 0x00002000 */
    	ori	r3,r3,LO(1<<(31-_PPC_MSR_BIT_FP))

	mtmsr	r3
	isync

    	/*
    	 * Floating Point Initialization
    	 *
    	 * Erratum #8 - Stfd of uninitialized FPR can hang part
    	 *
    	 * Overview:
    	 * An stfd of an uninitialized FPR can cause the part to 
    	 * hang, if the FPR has powered up in a certain state.
    	 *
    	 * Detailed Description:
    	 * The 64-bit FPRs each have an additional 6-bit field 
    	 * associated with them that specifies the type of floating 
    	 * point number that the register contains. This field gets 
    	 * properly set whenever the FPR is loaded. The part could
    	 * power up with some internal FPR bits randomly set such 
    	 * that the FPR is interpreted as containing a denormalized 
    	 * number, but with the mantissa contains all zeroes.  If 
    	 * this random state is stored out with an stfd before the 
    	 * internal bits are corrected via an FP load operation, 
    	 * the part will hang searching for a leading '1' in the 
    	 * mantissa.
    	 * The stfd is the only instruction that causes this behavior.
    	 * 
    	 * Solution:
    	 * Upon coming out of a Power-On-Reset (POR), initialize all 
    	 * of the FPRs that will be used. The value used for 
    	 * initialization is not important.

        /* Initialize the floating point control/status register */

        mtfsfi  7,0x0
        mtfsfi  6,0x0
        mtfsfi  5,0x0
        mtfsfi  4,0x0
        mtfsfi  3,0x0
        mtfsfi  2,0x0
        mtfsfi  1,0x0
        mtfsfi  0,0x0
        isync

        /* Initialize the floating point data registers */

        bl      ifpdr_value
        .long   0x3f800000      /* 1.0 */
ifpdr_value:
        mfspr   r3,LR
        lfs     f0,0(r3)
        lfs     f1,0(r3)
        lfs     f2,0(r3)
        lfs     f3,0(r3)
        lfs     f4,0(r3)
        lfs     f5,0(r3)
        lfs     f6,0(r3)
        lfs     f7,0(r3)
        lfs     f8,0(r3)
        lfs     f9,0(r3)
        lfs     f10,0(r3)
        lfs     f11,0(r3)
        lfs     f12,0(r3)
        lfs     f13,0(r3)
        lfs     f14,0(r3)
        lfs     f15,0(r3)
        lfs     f16,0(r3)
        lfs     f17,0(r3)
        lfs     f18,0(r3)
        lfs     f19,0(r3)
        lfs     f20,0(r3)
        lfs     f21,0(r3)
        lfs     f22,0(r3)
        lfs     f23,0(r3)
        lfs     f24,0(r3)
        lfs     f25,0(r3)
        lfs     f26,0(r3)
        lfs     f27,0(r3)
        lfs     f28,0(r3)
        lfs     f29,0(r3)
        lfs     f30,0(r3)
        lfs     f31,0(r3)
        sync

	/* Init the Segment registers */

	andi.	r3,r3,0
	mtsr	0,r3
	mtsr	1,r3
	mtsr	2,r3
	mtsr	3,r3
	mtsr	4,r3
	mtsr	5,r3
	mtsr	6,r3
	mtsr	7,r3
	mtsr	8,r3
	mtsr	9,r3
	mtsr	10,r3
	mtsr	11,r3
	mtsr	12,r3
	mtsr	13,r3
	mtsr	14,r3
	mtsr	15,r3
	isync

	/*
         * Hardware Data Cache Flush
         * 
         * If Arthur processor then skip the hardware data cache flush.
         *
         * If Nitro/Max processor then we must perform a hardware data 
         * cache flush.
         *
         * The recommended sequence to flush the data cache is:
         *   1. disable interrupts (N/A at this point)
         *   2. dssall
         *   3. sync
         *   4. set MSSCR0[DL1HWFLSH]=1
         *   5. sync
         * 
         * As per MPC7400 User's Manual "3.5.2 Data Cache Hardware
         * Flush Parameter in MSSCR0".(pg. 3-39)
         */

	mfspr	r28,PVR          /* Processor Version Register */
	rlwinm	r28,r28,16,16,31

	cmpwi	r28,CPU_TYPE_750
	bne	cacheFlush       /* skip flush and errata if arthur */

        bl      errataDone

cacheFlush:

#ifdef INCLUDE_ALTIVEC
        .long 0x7E00066C         /* Instruction for dssall */
#endif  /* INCLUDE_ALTIVEC */

        sync

	lis	r2,HI(DL1HWFLSH)
	ori	r2,r2,LO(DL1HWFLSH)
	mtspr	MSSCR0,r2			 /* MSSCR0 */

	/*
	 * required sync to guarantee that all data from the dL1 has
	 * been written to the system address interface.
	 */

	sync

        /* Apply errata fix for Nitro/Max */ 

        cmpli   0,0,r28,CPU_TYPE_NITRO
        bne     maxErrata             

        bl      nitroErrata
        
errataDone:

	/* 
	 * Turn on instruction cache - note that we must run with
	 * instruction cache turned on in order for sysMemParamConfig()
	 * to correctly compute the CPU bus speed, the bus speed
	 * algorithm fails if instuction cache is turned off.  The
	 * user normally controls instruction cache on or off with
	 * the USER_I_CACHE_ENABLE #define (which is turned on by
	 * default).  Even if USER_I_CACHE_ENABLE is #undef'ed we MUST
	 * have the instruction cache turned on when we execute
	 * sysMemParamConfig().  Just before leaving romInit.s to
	 * go to the C entry point, we turn off instruction cache
	 * and then conditionally turn it on based on the setting of
	 * USER_I_CACHE_ENABLE.  Thus, upon leaving romInit.s the
	 * instruction on/off state correctly reflects the setting
	 * of USER_I_CACHE_ENABLE.
	 */

	bl	iCacheOn		/* Turn on instruction cache */

	cmpli	0,0,r31,BOOT_COLD	/* check for warm boot */
	bc	4,2,skipMemGo		/* if warm boot, skip mem cntlr init */

	/* Turn off memory controller so we can make adjustments */

	bl	memCtlrOff

	/*
	 * Configure the memory	controller in a	default	setting	- just
	 * in case we cannot read SPD for optimal configuration.
	 */

	bl	mpc107DefInit		/* (mpc107DefInit - turn on MEMGO) */

	/*
	 * The memory controller should have just been programmed in
	 * such a way that we could use DRAM.  However, we will avoid
	 * using it for now by confining all of our access to RAM to
	 * be contained within the L1 cache in write-back mode.  All
	 * references within this space will not be flushed out to
	 * DRAM.  We accomplish this in the following manner:
	 *
	 * 1. Program the data BATs for memory management.  We
	 *    must have some type of memory management operating
	 *    if we are going to use data cache in copyback mode.
	 *    Use the first two DBATs to access the first 512MB
	 *    of system memory and the last two DBATs to access the 
	 *    PCI config space and memory controller registers.  This 
	 *    is necessary in order to configure the controller.  Once
	 *    the controller is programmed we no longer need the DBATs.
	 *
	 * 2. Invalidate the data cache and TLB entries.
	 *
	 * 4. Enable the data MMU.
	 *
	 * 5. Turn on the data cache.
	 *
	 * 6. Zero out some of the L1 data cache in the address range
	 *    occupied by the stack so that the cache tag entires are
	 *    present and all future stack access hit the L1 cache and
	 *    don't go out to DRAM.
	 */

	bl	setDbats

	/* DBAT contents arranged DBAT0L, DBAT0H, DBAT1L, ... */

	/* first 256 MB of RAM starting at 0x00000000 */

	.long	((0x00000000	& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |\
		_MMU_LBAT_GUARDED)
	.long	((0x00000000	&_MMU_UBAT_BEPI_MASK) |	_MMU_UBAT_BL_256M |\
		_MMU_UBAT_VS | _MMU_UBAT_VP)

	/* second 256 MB of RAM starting at 0x10000000 */

	.long	((0x10000000	& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |\
		_MMU_LBAT_GUARDED)
	.long	((0x10000000	& _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |\
		_MMU_UBAT_VS | _MMU_UBAT_VP)

	/* third 256 MB starting at 0x80000000 PrEP mode PCI config space */

	.long	((0x80000000	& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |\
		_MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED)
	.long	((0x80000000	& _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |\
		_MMU_UBAT_VS | _MMU_UBAT_VP)

	/* 256 MB of MPC107 register and FLASH ROM space */

	.long	((0xf0000000	& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |\
		_MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED)
	.long	((0xf0000000	& _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M |\
		_MMU_UBAT_VS | _MMU_UBAT_VP)