sysalib.s

This file contains board-specific information for the Motorola LoPEC in support of the lopec BSP. S

/***************************************************************************
*
* sysPciInWord - reads a word from PCI I/O or Memory space
*
* This function	reads a	word from a specified PCI I/O or Memory	address
* via the PCI bridge chip. This	function should	be used	for access
* to the I/O or	Memory mapped registers	of a PCI device. These
* registers are	mapped as little-endian,so we byte swap	the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: word	from address.
*
* UINT16 sysPciInWord (UINT16 *	dataPtr)
*
* NOMANUAL
*/

FUNC_BEGIN(sysPciInWord)
FUNC_BEGIN(sysInWord)
	lhbrx	r3,r0,r3        /* Read word from address */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciInWord)
FUNC_END(sysInWord)


/***************************************************************************
*
* sysPciOutWord	- writes a word	to PCI I/O or Memory space
*
* This function	writes a word to a specified PCI I/O or	Memory address
* via the PCI bridge chip. This	function should	be used	for access
* to the I/O or	Memory mapped registers	of a PCI device. These
* registers are	mapped as little-endian,so we byte swap	the data in order
* to make the value written correct for	the registers in PCI space.
*
* RETURNS: N/A
*
* void sysPciOutWord (UINT16 * dataPtr,UINT16 data)
*
* NOMANUAL
*/

FUNC_BEGIN(sysPciOutWord)
FUNC_BEGIN(sysOutWord)
	sthbrx	r4,r0,r3        /* Write a word to the address */
	sync                    /* Sync I/O operation */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciOutWord)
FUNC_END(sysOutWord)


/***************************************************************************
*
* sysPciInLong - reads a longword from PCI I/O or Memory space
*
* This function	reads a	longword from a	specified PCI I/O or Memory address
* via the PCI bridge chip. This	function should	be used	for access
* to the I/O or	Memory mapped registers	of a PCI device. These
* registers are	mapped as little-endian,so we byte reverse the data in order
* to make the value returned look the same as it would in PCI space.
*
* RETURNS: longword from address.
*
* UINT32 sysPciInLong (UINT32 *	dataPtr)
*
* NOMANUAL
*/

FUNC_BEGIN(sysPciInLong)
FUNC_BEGIN(sysInLong)
	lwbrx	r3,r0,r3        /* Read longword reverse bytes */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciInLong)
FUNC_END(sysInLong)


/***************************************************************************
*
* sysPciOutLong	- writes a longword to PCI I/O or Memory space
*
* This function	writes a longword to a specified PCI I/O or Memory address
* via the PCI bridge chip. This	function should	be used	for access
* to the I/O or	Memory mapped registers	of a PCI device. These
* registers are	mapped as little-endian,so we byte reverse the data in order
* to make the value written correct for	the registers in PCI space.
*
* RETURNS: N/A
*
* void sysPciOutLong (UINT32 * dataPtr,UINT32 data)
*
* NOMANUAL
*/


FUNC_BEGIN(sysPciOutLong)
FUNC_BEGIN(sysOutLong)
	stwbrx	r4,r0,r3        /* Write longword reverse bytes */
	sync                    /* Sync I/O operation */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciOutLong)
FUNC_END(sysOutLong)


/***************************************************************************
*
* sysMemProbeSup - sysBusProbe support routine
*
* This routine is called to try	to read	byte,word,or long,as specified
* by length,from the specified source to the specified destination.
*
* RETURNS: OK if successful probe,else ERROR
*
* STATUS sysMemProbeSup (length,src,dest)
*     (
*     int length,// length of	cell to	test (1,2,4,8,16) *
*     char * src,// address to read *
*     char * dest // address to write	*
*     )
*
* NOMANUAL
*/

FUNC_BEGIN(sysMemProbeSup)
	addi	p7,p0,0		/* save length to p7 */
	xor	p0,p0,p0 	/* set return status */
	cmpwi	p7,1 		/* check for byte access */
	bne	sbpShort 	/* no,go check for short word access */
	lbz	p6,0(p1) 	/* load byte from source */
	stb	p6,0(p2) 	/* store byte to destination */
	sync
	isync			/* enforce for immediate exception handling */
	blr
sbpShort:
	cmpwi	p7,2 		/* check for short word access */
	bne	sbpWord		/* no,check for word access */
	lhz	p6,0(p1) 	/* load half word from source */
	sth	p6,0(p2) 	/* store half word to destination */
	sync
	isync			/* enforce for immediate exception handling */
	blr
sbpWord:
	cmpwi	p7,4 		/* check for short word access */
	bne	sysProbeExc 	/* no,check for double word access */
	lwz	p6,0(p1) 	/* load half word from source */
	stw	p6,0(p2) 	/* store half word to destination */
	sync
	isync			/* enforce for immediate exception handling */
	blr
sysProbeExc:
	li	p0,-1 		/* shouldn't ever get here,but... */
	blr

FUNC_END(sysMemProbeSup)


/***************************************************************************
*
* sysTimeBaseLGet - Get	lower half of Time Base	Register
*
* This routine will read the contents the lower	half of	the Time
* Base Register	(TBL - TBR 268).
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT32 sysTimeBaseLGet(void)
*
* RETURNS: value of TBR	268 (in	r3)
*
* NOMANUAL
*/

FUNC_BEGIN(sysTimeBaseLGet)
	mftb	3
	bclr	20,0
FUNC_END(sysTimeBaseLGet)


/***************************************************************************
*
* sysL2crPut - write to	L2CR register of Arthur	CPU
*
* This routine will write the contents of r3 to	the L2CR
* register.
* )
* From a C point of view,the routine is	defined	as follows:
*
* void sysL2crPut
* (
* ULONG	value to write
* )
*
* RETURNS: NA
*
* NOMANUAL
*/

FUNC_BEGIN(sysL2crPut)
	mtspr	L2CR_REG,r3
	bclr	20,0 		/* Return to caller */
FUNC_END(sysL2crPut)


/***************************************************************************
*
* sysL2crGet - read from L2CR register of Arthur CPU
*
* This routine will read the contents the L2CR register.
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT sysL2crGet()
*
* RETURNS: value of SPR1017 (in	r3)
*
* NOMANUAL
*/

FUNC_BEGIN(sysL2crGet)
	mfspr	r3,L2CR_REG
	bclr	20,0 		/* Return to caller */
FUNC_END(sysL2crGet)


/***************************************************************************
*
* sysL2pmcrPut - write to the L2PMCR (Private Memory Control Register) of
*                Nitro CPU
*
* This routine will write the contents of r3 to	the L2PMCR
* register.
* 
* From a C point of view,the routine is	defined	as follows:
*
* void sysL2pmcrPut
* (
* ULONG	value to write
* )
*
* RETURNS: NA
*
* NOMANUAL
*/

FUNC_BEGIN(sysL2pmcrPut)
        mtspr   L2PMCR,r3
        bclr    20,0            /* Return to caller */
FUNC_END(sysL2pmcrPut)


/***************************************************************************
*
* sysL2pmcrGet - read from L2PMCR (Private Memory Control Register)  
*                of the Nitro CPU
*
* This routine will read the contents the L2PMCR register.
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT sysL2pmcrGet()
*
* RETURNS: value of SPR1016 (in	r3)
*
* NOMANUAL
*/

FUNC_BEGIN(sysL2pmcrGet)
        mfspr   r3,L2PMCR
        bclr    20,0            /* Return to caller */
FUNC_END(sysL2pmcrGet)


/***************************************************************************
*
* sysHid1Get - read from HID1 register SPR1009.
*
* This routine will return the contents	of the HID1 (SPR1009)
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT sysHid1Get()
*
* RETURNS: value of SPR1009 (in	r3)
*
* NOMANUAL
*/

FUNC_BEGIN(sysHid1Get)
	mfspr	r3,HID1
	bclr	20,0
FUNC_END(sysHid1Get)


/***************************************************************************
*
* sysHid2Get - read from HID2 register SPR1011.
*
* This routine will return the contents	of the HID2 (SPR1011)
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT sysHid2Get()
*
* RETURNS: value of SPR1011 (in	r3)
*
* NOMANUAL
*/

FUNC_BEGIN(sysHid2Get)
	mfspr	r3,HID2
	bclr	20,0
FUNC_END(sysHid2Get)


/***************************************************************************
*
* sysHid2Set - write data to HID2 register SPR1011.
*
* This routine will store the contents of HID2 (SPR1011) with the data
* supplied in R3.
*
* From a C point of view,the routine is	defined	as follows:
*
* UINT sysHid2Set(UINT dataValue)
*
* RETURNS: N/A
*
* NOMANUAL
*/

FUNC_BEGIN(sysHid2Set)
	mtspr	HID2,r3
	bclr	20,0
FUNC_END(sysHid2Set)


/***************************************************************************
*
* maxErrata - apply relevant errata workarounds for Max processor.
*
* RETURNS: N/A
*
* NOMANUAL
*/

FUNC_BEGIN(maxErrata)

	/* Get the MAX revision type. If 2.7 or less apply errata fix. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,7
	bc	12,5,cpuNotMax27	/* branch if greater than 7 */

	/*
	 * The following five instructions is a	workaround for errata #13
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips", Errata Version 9	6/27/00.  Description: "Speculative
	 * instruction stream may cause	duplicate data cache tags".
	 */

	li	r2,0x0
	mtspr	MSSCR0,r2			/* MSSCR0 */

	lis	r2,HI(MEMSSCR1)
	ori	r2,r2,LO(MEMSSCR1)	/* MSSCR1: L1OPQ_SIZE=0x01000000 */
	mtspr	MSSCR1,r2

	/*
	 * The following five instructions is a	workaround for errata #7
	 * as described	in "PowerPC Max	Microprocessor Errata List Release
	 * 2.x Chips",Errata Version 9 6/27/00.	Description: "Store data
	 * lost	when store gathering is	enabled	during cache ops".
	 */

	mfspr	r2,HID0
	lis	r3,HI(SGE_CLEAR)	/* SGE: clear */
	ori	r3,r3,LO(SGE_CLEAR)
	andc	r2,r2,r3
	mtspr	HID0,r2

cpuNotMax27:

	bclr	20,0

FUNC_END(maxErrata)


/***************************************************************************
*
* nitroErrata - apply relevant errata workarounds for Nitro processor.
*
* RETURNS: N/A
*
* NOMANUAL
*/

FUNC_BEGIN(nitroErrata)

	/* Get the NITRO revision type. */

	mfspr	r29,PVR
	rlwinm	r29,r29,0,24,31

	cmpwi	r29,(CPU_REV_NITRO+2)
	bc	12,5,errataDone		/* branch if greater than 0x1102 */

	/*
	 * The following five instructions is a	workaround for errata #1
	 * as described	in "PowerPC Nitro Microprocessor Errata	List Release
	 * 1.x Chips",Errata Version 3 3/29/00.	Description: "Cache inhibited
	 * instruction fetches that hit	in L2 Direct Mapped SRAM space may
	 * cause processor hang".
	 */

	li	r2,0x0
	mtspr	MSSCR0,r2			/* MSSCR0 */

	lis	r2,HI(MEMSSCR1_NITRO)
	ori	r2,r2,LO(MEMSSCR1_NITRO)	/* MSSCR1: Nitro errata 1 */
	mtspr	MSSCR1,r2

	bclr	20,0

FUNC_END(nitroErrata)