sysalib.s

This file contains board-specific information for the Motorola LoPEC in support of the lopec BSP. S

/* sysALib.s - Motorola LoPEC system-dependent assembly routines */

/* Copyright 1984-2002 Wind River Systems,Inc. */
/* Copyright 1996-2002 Motorola,Inc. All Rights Reserved */
	.data
	.globl copyright_wind_river
	.long copyright_wind_river

/*
modification history
--------------------
01h,18jul02,mil Added errata workaround when disabling L2.
01g,23may02,mil Turned off L2 cache in sysInit (SPR #72214).
01f,18mar02,mil Merged from T2.1 to T2.2, updated directives.
01e,19oct01,cak Modified as per Wind River code review.
01d,22jan01,scb removed not needed sysPciConfig...() routines.
01c,07dec00,scb consolidated errata into callable functions, matching romInit.s
01b,20nov00,scb	Processor support
01a,02nov00,djs	created	based on 01g,08feb00,rhk mv2100
*/

/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.

This module must be the	first specified	in the \f3ld\f1	command	used to
build the system. The sysInit()	routine	is the system start-up code.
*/

/* defines */

#define	_ASMLANGUAGE

/* Special Purpose Registers */

#define HID1    1009    /* HID1 - Hardware Implementation Dependent Reg. 1 */
#define HID2    1011    /* HID2 - Hardware Implementation Dependent Reg. 2 */
#define MSSCR0  1014    /* MSSCR0 - Memory Subsystem Control Register 0 */
#define MSSCR1  1015    /* MSSCR1 - Memory Subsystem Control Register 1 */
#define LR      8       /* LR - Link Register */
#define CTR     9       /* CTR - Count Register */
#define DEC     22      /* DEC - Decrementer */
#define L2PMCR  1016    /* L2PMCR - L2 Private Memory Control Register */

#define	SGE_CLEAR 0x00000080 		/* SGE: clear */
#define	MEMSSCR1 0x01000000 		/* Max Memory SubSystem Control Reg 1 */
#define	MEMSSCR1_NITRO 0x00040000 	/* Nitro Mem SubSystem Control Reg 1 */
#define	DL1HWFLSH 0x00800000 		/* L1 data cache HW flush bit 8 */

#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"
#include "asm.h"
#include "sysCache.h"

	/* globals */

	FUNC_EXPORT(_sysInit)		/* start of system code */
	FUNC_EXPORT(sysInByte)
	FUNC_EXPORT(sysOutByte)
	FUNC_EXPORT(sysPciInByte)
	FUNC_EXPORT(sysPciOutByte)
	FUNC_EXPORT(sysInWord)
	FUNC_EXPORT(sysInWordRev)
	FUNC_EXPORT(sysOutWord)
	FUNC_EXPORT(sysPciInWord)
	FUNC_EXPORT(sysPciOutWord)
	FUNC_EXPORT(sysInLong)
	FUNC_EXPORT(sysOutLong)
	FUNC_EXPORT(sysPciInLong)
	FUNC_EXPORT(sysPciOutLong)
	FUNC_EXPORT(sysMemProbeSup)
	FUNC_EXPORT(sysProbeExc)
	FUNC_EXPORT(sysL2crPut)
	FUNC_EXPORT(sysL2crGet)
	FUNC_EXPORT(sysL2pmcrPut)
	FUNC_EXPORT(sysL2pmcrGet)
	FUNC_EXPORT(sysTimeBaseLGet)
	FUNC_EXPORT(sysHid1Get)
	FUNC_EXPORT(sysHid2Set)
	FUNC_EXPORT(sysHid2Get)

	/* externals */

	FUNC_IMPORT(usrInit)

	_WRS_TEXT_SEG_START

/***************************************************************************
*
* sysInit - start after boot
*
* SYNOPSIS
* \ss
* void sysInit
*     (
*     void
*     )
* \se
*
* INCLUDE FILES: none
*
* RETURNS: N/A
*
* This is the system start-up entry point for VxWorks in RAM,the
* first	code executed after booting. It	disables interrupts,sets up
* the stack,and	jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down	from the address of sysInit(). This
* stack	is used	only by	usrInit() and is never used again. Memory for the
* stack	must be	accounted for when determining the system load address.
*
* NOTE:	This routine should not	be called by the user.
*
*/

FUNC_BEGIN(_sysInit)

	/* disable external interrupts */

	xor	p0,p0,p0
	mtmsr	p0			/* clear the MSR register */

	/* return from decrementer exceptions */

	addis	p1,r0,0x4c00
	addi	p1,p1,0x0064		/* load rfi (0x4c000064) to p1 */
	stw	p1,0x900(r0)		/* store rfi at 0x00000900 */

	/* initialize the stack pointer */

	lis	sp,HIADJ(RAM_LOW_ADRS)
	addi	sp,sp,LO(RAM_LOW_ADRS)

	mfspr	r28,PVR                /* Processor Version Register */
	rlwinm	r28,r28,16,16,31

	cmpwi	r28,CPU_TYPE_750
	bne     cacheFlush     	       /* skip flush and errata if arthur */	

        bl      errataDone

cacheFlush:

#ifdef INCLUDE_ALTIVEC
        .long   0x7E00066C             /* dssall instruction */
#endif  /* INCLUDE_ALTIVEC */

        sync

	lis	r2,HI(DL1HWFLSH)
	ori	r2,r2,LO(DL1HWFLSH)
	mtspr	MSSCR0,r2		/* MSSCR0 */

	/*
	 * required sync to guarantee that all data from the dL1 has
	 * been written to the system address interface.
	 */

	sync

        /* Apply errata fix for Nitro/Max */
        
	cmpli	0,0,r28,CPU_TYPE_NITRO
	bne     maxErrata	

        bl      nitroErrata

errataDone:

        /* disable unified L2 without flushing */

        /*
         * problem observed on Nitro rev 1.3, see errata #1
         * employing workaround from sysMaxL2Disable
         */
        mfspr   r3,L2CR_REG
        rlwinm  r3, r3, 0, 1,31
        sync
        b preFetchL2DisableCode

codeIsPrefetched:
        mtspr  L2CR_REG,r3
        sync
        isync

        b pastFetchL2DisableCode

preFetchL2DisableCode:
        sync
        isync
        b codeIsPrefetched

pastFetchL2DisableCode:

	/* Enable and invalidate both caches */

	mfspr	r3,HID0
	ori	r3,r3,(_PPC_HID0_ICFI |	_PPC_HID0_DCFI)
	ori	r3,r3,(_PPC_HID0_ICE | _PPC_HID0_DCE)
	sync		/* required before changing DCE */
	isync		/* required before changing ICE */
	mtspr	HID0, r3

	/*
	 * enable the branch history table, unlock both caches, disable the
	 * data cache and optionally disable the instruction cache.
	 */

	ori	r3,r3,_PPC_HID0_BHTE

#ifdef USER_I_CACHE_ENABLE
	rlwinm	r3,r3,0,_PPC_HID0_BIT_DLOCK+1,_PPC_HID0_BIT_DCE-1
#else
	rlwinm	r3,r3,0,_PPC_HID0_BIT_DLOCK+1,_PPC_HID0_BIT_ICE-1
#endif

	sync		/* required before changing DCE */
	isync		/* required before changing ICE */
	mtspr	HID0,r3

	/* disable instruction and data translations in the MMU */

	sync
	mfmsr	r3 	/* get the value in msr *

	/* clear bits IR and DR */

	rlwinm	r4,r3,0,_PPC_MSR_BIT_DR+1,_PPC_MSR_BIT_IR-1

	mtmsr	r4 	/* set the msr */
	isync 		/* flush inst. pipe and re-fetch */

	/* initialize the BAT register */

	li	p3,0 		/* clear p0 */

	isync
	mtspr	IBAT0U,p3	/* SPR 528 (IBAT0U) */
	isync

	mtspr	IBAT0L,p3 	/* SPR 529 (IBAT0L) */
	isync

	mtspr	IBAT1U,p3 	/* SPR 530 (IBAT1U) */
	isync

	mtspr	IBAT1L,p3 	/* SPR 531 (IBAT1L) */
	isync

	mtspr	IBAT2U,p3 	/* SPR 532 (IBAT2U) */
	isync

	mtspr	IBAT2L,p3 	/* SPR 533 (IBAT2L) */
	isync

	mtspr	IBAT3U,p3 	/* SPR 534 (IBAT3U) */
	isync

	mtspr	IBAT3L,p3 	/* SPR 535 (IBAT3L) */
	isync

	mtspr	DBAT0U,p3 	/* SPR 536 (DBAT0U) */
	isync

	mtspr	DBAT0L,p3 	/* SPR 537 (DBAT0L) */
	isync

	mtspr	DBAT1U,p3 	/* SPR 538 (DBAT1U) */
	isync

	mtspr	DBAT1L,p3 	/* SPR 539 (DBAT1L) */
	isync

	mtspr	DBAT2U,p3 	/* SPR 540 (DBAT2U) */
	isync

	mtspr	DBAT2L,p3 	/* SPR 541 (DBAT2L) */
	isync

	mtspr	DBAT3U,p3 	/* SPR 542 (DBAT3U) */
	isync

	mtspr	DBAT3L,p3 	/* SPR 543 (DBAT3L) */
	isync

	/* invalidate entries within both TLBs */

	li	p1,128
	xor	p0,p0,p0 	/* p0 = 0 */
	mtctr	p1 		/* CTR = 32 */

	isync			/* context sync req'd before tlbie */
sysALoop:
	tlbie	p0
	addi	p0,p0,0x1000 	/* increment bits 15-19 */
	bdnz	sysALoop 	/* decrement CTR,branch if CTR != 0 */
	sync 			/* sync instr req'd after tlbie */

	/* initialize Small Data Area (SDA) start address */

#if FALSE /* XXX TPR NO SDA for now */
	lis	r2,HIADJ(_SDA2_BASE_)
	addi	r2,r2,LO(_SDA2_BASE_)

	lis	r13,HIADJ(_SDA_BASE_)
	addi	r13,r13,LO(_SDA_BASE_)
#endif

	addi	sp,sp,-FRAMEBASESZ 	/* get frame stack */
	li	r3,BOOT_WARM_AUTOBOOT
	b	usrInit			/* never returns - starts up kernel */

FUNC_END(_sysInit)


/***************************************************************************
*
* sysInByte - reads a byte from	an io address.
*
* This function	reads a	byte from a specified io address or from local memory.
* It operates in big-endian mode and does not perform any translation
* operations on	either the supplied address or the retrieved data.
*
* RETURNS: byte	from address.
*
* UINT8	sysInByte (UINT8 * dataPtr)
*
* NOMANUAL
*/

FUNC_BEGIN(sysInByte)
        isync
	lbzx	r3,r0,r3        /* Read byte from address */
	bclr	20,0            /* Return to caller */
FUNC_END(sysInByte)


/***************************************************************************
*
* sysOutByte - writes a	byte to	an io address.
*
* This function	writes a byte to a specified io	address	or to local memory.
* It operates in big-endian mode and does not perform any translation
* operations on	either the supplied address or data.
*
* RETURNS: N/A
*
* void sysOutByte (UINT8 * dataPtr,UINT8 data)
*
* NOMANUAL
*/

FUNC_BEGIN(sysOutByte)
	stbx	r4,r0,r3        /* Write a byte to address */
	sync                    /* Sync I/O operation */
	bclr	20,0            /* Return to caller */
FUNC_END(sysOutByte)


/***************************************************************************
*
* sysPciInByte - reads a byte from PCI I/O or Memory space
*
* This function	reads a	byte from a specified PCI I/O or Memory	address
* via the PCI bridge chip. This	function should	be used	for access
* to the I/O or	Memory mapped registers	of a PCI device. Since this routine
* accesses only	a single byte of data no address or data manipulation is
* required.
*
* RETURNS: byte	from address.
*
* UINT8	sysPciInByte (UINT8 * dataPtr)
*
* NOMANUAL
*/

FUNC_BEGIN(sysPciInByte)
        isync
	lbzx	r3,r0,r3        /* Read byte from address */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciInByte)


/***************************************************************************
*
* sysPciOutByte	- writes a byte	to PCI I/O or Memory space
*
* This function	writes a byte to a specified PCI I/O or	Memory address
* via the QSPAN	bridge chip. This function should be used for writing
* to the I/O or	Memory mapped registers	of a PCI device. Since this routine
* writes only a	single byte of data no address or data manipulation is
* required.
*
* RETURNS: N/A
*
* void sysPciOutByte (UINT8 * dataPtr,UINT8 data)
*
* NOMANUAL
*/

FUNC_BEGIN(sysPciOutByte)
	stbx	r4,r0,r3        /* Write a byte to address */
	sync                    /* Sync I/O operation */
	bclr	20,0            /* Return to caller */
FUNC_END(sysPciOutByte)


/***************************************************************************
*
* sysInWordRev - reads a word (16-bit byte reversed) from an io	address.
*
* This function	reads a	word from a specified io address,or memory
* and reverses the bytes.
*
* RETURNS: 16 bit word (byte swapped) read from	address
*
* UINT16 sysInWordRev (UINT16 *	dataPtr)
*
* NOMANUAL
*/

FUNC_BEGIN(sysInWordRev)
	lhbrx	r3,r0,r3        /* Read word from address */
	bclr	20,0            /* Return to caller */
FUNC_END(sysInWordRev)