xgate.cxgate

XGATE Training2_Xgate_Software_Interrupts

#include <hidef.h>      /* common defines and macros */
#include "xgate.h"
#include <MC9S12XEP100.h> 



#pragma push
#pragma DATA_SEG SHARED_DATA
extern unsigned char Variable0;
extern unsigned char Variable1;
#pragma pop

// interrupt handler
interrupt void SoftwareTrigger0_Handler(int dummy)
{
 volatile unsigned char localarray[3];
 localarray[0]=0xAA;
 localarray[1]=0xAA;
 localarray[2]=0xAA;
 
 Variable0=1;
 
 
 //trigger software trigger1
 XGSWT=0x0202;
 

 
 //this infinite loop is here to prove that 
 //the only way SWT1 gets to be executed is by interrupting SWT0. 
 for(;;);
}

// interrupt handler
interrupt void SoftwareTrigger1_Handler(int dummy)
{
  
 volatile unsigned char localarray[3];
 localarray[0]=0xBB;
 localarray[1]=0xBB;
 localarray[2]=0xBB;
  
  Variable1=1;
  
  //clear software trigger 1 flag
  XGSWT=0x0200;
  
}

// interrupt handler for all others
interrupt void ErrorHandler(int chanNum)
{
  asm BRK;
}

#pragma CONST_SEG XGATE_VECTORS  

const XGATE_TableEntry XGATE_VectorTable[] = {
                         // Channel # = Vector address / 2
  /* channel 0..0x1D are not used by Xgate in this device.First used channel number must match macro XGATE_VECTOR_OFFSET in xgate.h */

  {ErrorHandler, 0x1E},  // Channel 1E - ATD1 Compare Interrupt
  {ErrorHandler, 0x1F},  // Channel 1F - ATD0 Compare Interrupt
  {ErrorHandler, 0x20},  // Channel 20 - TIM Pulse Accumulator input edge
  {ErrorHandler, 0x21},  // Channel 21 - TIM Pulse Accumulator A Overflow
  {ErrorHandler, 0x22},  // Channel 22 - TIM Overflow
  {ErrorHandler, 0x23},  // Channel 23 - TIM Channel 7
  {ErrorHandler, 0x24},  // Channel 24 - TIM Channel 6
  {ErrorHandler, 0x25},  // Channel 25 - TIM Channel 5
  {ErrorHandler, 0x26},  // Channel 26 - TIM Channel 4
  {ErrorHandler, 0x27},  // Channel 27 - TIM Channel 3
  {ErrorHandler, 0x28},  // Channel 28 - TIM Channel 2
  {ErrorHandler, 0x29},  // Channel 29 - TIM Channel 1
  {ErrorHandler, 0x2A},  // Channel 2A - TIM Channel 0
  {ErrorHandler, 0x2B},  // Channel 2B - SCI7
  {ErrorHandler, 0x2C},  // Channel 2C - PIT Channel 7
  {ErrorHandler, 0x2D},  // Channel 2D - PIT Channel 6
  {ErrorHandler, 0x2E},  // Channel 2E - PIT Channel 5
  {ErrorHandler, 0x2F},  // Channel 2F - PIT Channel 4
  {ErrorHandler, 0x30},  // Channel 30 - Reserved
  {ErrorHandler, 0x31},  // Channel 31 - Reserved    
  {ErrorHandler, 0x32},  // Channel 32 - XGATE Software Trigger 7           
  {ErrorHandler, 0x33},  // Channel 33 - XGATE Software Trigger 6           
  {ErrorHandler, 0x34},  // Channel 34 - XGATE Software Trigger 5           
  {ErrorHandler, 0x35},  // Channel 35 - XGATE Software Trigger 4           
  {ErrorHandler, 0x36},  // Channel 36 - XGATE Software Trigger 3           
  {ErrorHandler, 0x37},  // Channel 37 - XGATE Software Trigger 2           
  {(XGATE_Function)SoftwareTrigger1_Handler, 0x38},  // Channel 38 - XGATE Software Trigger 1           
  {(XGATE_Function)SoftwareTrigger0_Handler, 0x39},  // Channel 39 - XGATE Software Trigger 0       
  {ErrorHandler, 0x3A},  // Channel 3A - Periodic Interrupt Timer           
  {ErrorHandler, 0x3B},  // Channel 3B - Periodic Interrupt Timer           
  {ErrorHandler, 0x3C},  // Channel 3C - Periodic Interrupt Timer           
  {ErrorHandler, 0x3D},  // Channel 3D - Periodic Interrupt Timer           
  {ErrorHandler, 0x3E},  // Channel 3E - Reserved                           
  {ErrorHandler, 0x3F},  // Channel 3F - Autonomous Periodical interrupt API
  {ErrorHandler, 0x40},  // Channel 40 - Low Voltage interrupt LVI
  {ErrorHandler, 0x41},  // Channel 41 - IIC1 Bus                 
  {ErrorHandler, 0x42},  // Channel 42 - SCI5                     
  {ErrorHandler, 0x43},  // Channel 43 - SCI4                     
  {ErrorHandler, 0x44},  // Channel 44 - SCI3                     
  {ErrorHandler, 0x45},  // Channel 45 - SCI2                     
  {ErrorHandler, 0x46},  // Channel 46 - PWM Emergency Shutdown   
  {ErrorHandler, 0x47},  // Channel 47 - Port P Interrupt         
  {ErrorHandler, 0x48},  // Channel 48 - CAN4 transmit            
  {ErrorHandler, 0x49},  // Channel 49 - CAN4 receive             
  {ErrorHandler, 0x4A},  // Channel 4A - CAN4 errors              
  {ErrorHandler, 0x4B},  // Channel 4B - CAN4 wake-up             
  {ErrorHandler, 0x4C},  // Channel 4C - CAN3 transmit            
  {ErrorHandler, 0x4D},  // Channel 4D - CAN3 receive             
  {ErrorHandler, 0x4E},  // Channel 4E - CAN3 errors              
  {ErrorHandler, 0x4F},  // Channel 4F - CAN3 wake-up             
  {ErrorHandler, 0x50},  // Channel 50 - CAN2 transmit
  {ErrorHandler, 0x51},  // Channel 51 - CAN2 receive 
  {ErrorHandler, 0x52},  // Channel 52 - CAN2 errors  
  {ErrorHandler, 0x53},  // Channel 53 - CAN2 wake-up 
  {ErrorHandler, 0x54},  // Channel 54 - CAN1 transmit
  {ErrorHandler, 0x55},  // Channel 55 - CAN1 receive 
  {ErrorHandler, 0x56},  // Channel 56 - CAN1 errors  
  {ErrorHandler, 0x57},  // Channel 57 - CAN1 wake-up 
  {ErrorHandler, 0x58},  // Channel 58 - CAN0 transmit
  {ErrorHandler, 0x59},  // Channel 59 - CAN0 receive 
  {ErrorHandler, 0x5A},  // Channel 5A - CAN0 errors  
  {ErrorHandler, 0x5B},  // Channel 5B - CAN0 wake-up 
  {ErrorHandler, 0x5C},  // Channel 5C - FLASH 
  {ErrorHandler, 0x5D},  // Channel 5D - EEPROM
  {ErrorHandler, 0x5E},  // Channel 5E - SPI2  
  {ErrorHandler, 0x5F},  // Channel 5F - SPI1
  {ErrorHandler, 0x60},  // Channel 60 - IIC0 Bus                         
  {ErrorHandler, 0x61},  // Channel 61 - SCI6                        
  {ErrorHandler, 0x62},  // Channel 62 - CRG Self Clock Mode              
  {ErrorHandler, 0x63},  // Channel 63 - CRG PLL lock                     
  {ErrorHandler, 0x64},  // Channel 64 - Pulse Accumulator B Overflow     
  {ErrorHandler, 0x65},  // Channel 65 - Modulus Down Counter underflow   
  {ErrorHandler, 0x66},  // Channel 66 - Port H                           
  {ErrorHandler, 0x67},  // Channel 67 - Port J                           
  {ErrorHandler, 0x68},  // Channel 68 - ATD1                             
  {ErrorHandler, 0x69},  // Channel 69 - ATD0                             
  {ErrorHandler, 0x6A},  // Channel 6A - SCI1                             
  {ErrorHandler, 0x6B},  // Channel 6B - SCI0                             
  {ErrorHandler, 0x6C},  // Channel 6C - SPI0                             
  {ErrorHandler, 0x6D},  // Channel 6D - Pulse accumulator input edge     
  {ErrorHandler, 0x6E},  // Channel 6E - Pulse accumulator A overflow     
  {ErrorHandler, 0x6F},  // Channel 6F - Enhanced Capture Timer overflow  
  {ErrorHandler, 0x70},  // Channel 70 - Enhanced Capture Timer channel 7                                 
  {ErrorHandler, 0x71},  // Channel 71 - Enhanced Capture Timer channel 6 
  {ErrorHandler, 0x72},  // Channel 72 - Enhanced Capture Timer channel 5 
  {ErrorHandler, 0x73},  // Channel 73 - Enhanced Capture Timer channel 4 
  {ErrorHandler, 0x74},  // Channel 74 - Enhanced Capture Timer channel 3 
  {ErrorHandler, 0x75},  // Channel 75 - Enhanced Capture Timer channel 2 
  {ErrorHandler, 0x76},  // Channel 76 - Enhanced Capture Timer channel 1 
  {ErrorHandler, 0x77},  // Channel 77 - Enhanced Capture Timer channel 0 
  {ErrorHandler, 0x78},  // Channel 78 - Real Time Interrupt 
  
  };