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00179 *data++ = SPDR;00180 } 00181 <span class="comment">// release CS</span>00182 ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);00183 }00184 <a name="l00185"></a><a class="code" href="group__enc28j60.html#ga3">00185</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga3">enc28j60WriteBuffer</a>(u16 len, u08* data)00186 {00187 <span class="comment">// assert CS</span>00188 ENC28J60_CONTROL_PORT &= ~(1<<ENC28J60_CONTROL_CS);00189 00190 <span class="comment">// issue write command</span>00191 SPDR = ENC28J60_WRITE_BUF_MEM;00192 <span class="keywordflow">while</span>(!(SPSR & (1<<SPIF)));00193 <span class="keywordflow">while</span>(len--)00194 {00195 <span class="comment">// write data</span>00196 SPDR = *data++;00197 <span class="keywordflow">while</span>(!(SPSR & (1<<SPIF)));00198 } 00199 <span class="comment">// release CS</span>00200 ENC28J60_CONTROL_PORT |= (1<<ENC28J60_CONTROL_CS);00201 }00202 <a name="l00203"></a><a class="code" href="group__enc28j60.html#ga4">00203</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(u08 address)00204 {00205 <span class="comment">// set the bank (if needed)</span>00206 <span class="keywordflow">if</span>((address & BANK_MASK) != Enc28j60Bank)00207 {00208 <span class="comment">// set the bank</span>00209 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));00210 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);00211 Enc28j60Bank = (address & BANK_MASK);00212 }00213 }00214 <a name="l00215"></a><a class="code" href="group__enc28j60.html#ga5">00215</a> u08 <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(u08 address)00216 {00217 <span class="comment">// set the bank</span>00218 <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address);00219 <span class="comment">// do the read</span>00220 <span class="keywordflow">return</span> <a class="code" href="group__enc28j60.html#ga0">enc28j60ReadOp</a>(ENC28J60_READ_CTRL_REG, address);00221 }00222 <a name="l00223"></a><a class="code" href="group__enc28j60.html#ga6">00223</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(u08 address, u08 data)00224 {00225 <span class="comment">// set the bank</span>00226 <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(address);00227 <span class="comment">// do the write</span>00228 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_WRITE_CTRL_REG, address, data);00229 }00230 <a name="l00231"></a><a class="code" href="group__enc28j60.html#ga7">00231</a> u16 <a class="code" href="group__enc28j60.html#ga7">enc28j60PhyRead</a>(u08 address)00232 {00233 u16 data;00234 00235 <span class="comment">// Set the right address and start the register read operation</span>00236 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address);00237 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, MICMD_MIIRD);00238 00239 <span class="comment">// wait until the PHY read completes</span>00240 <span class="keywordflow">while</span>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) & MISTAT_BUSY);00241 00242 <span class="comment">// quit reading</span>00243 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MICMD, 0x00);00244 00245 <span class="comment">// get data value</span>00246 data = <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDL);00247 data |= <a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MIRDH);00248 <span class="comment">// return the data</span>00249 <span class="keywordflow">return</span> data;00250 }00251 <a name="l00252"></a><a class="code" href="group__enc28j60.html#ga8">00252</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(u08 address, u16 data)00253 {00254 <span class="comment">// set the PHY register address</span>00255 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIREGADR, address);00256 00257 <span class="comment">// write the PHY data</span>00258 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRL, data); 00259 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MIWRH, data>>8);00260 00261 <span class="comment">// wait until the PHY write completes</span>00262 <span class="keywordflow">while</span>(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(MISTAT) & MISTAT_BUSY);00263 }00264 <a name="l00265"></a><a class="code" href="group__enc28j60.html#ga9">00265</a> <span class="keywordtype">void</span> <a class="code" href="group__enc28j60.html#ga9">enc28j60Init</a>(<span class="keywordtype">void</span>)00266 {00267 <span class="comment">// initialize I/O</span>00268 sbi(ENC28J60_CONTROL_DDR, ENC28J60_CONTROL_CS);00269 sbi(ENC28J60_CONTROL_PORT, ENC28J60_CONTROL_CS);00270 00271 <span class="comment">// setup SPI I/O pins</span>00272 sbi(ENC28J60_SPI_PORT, ENC28J60_SPI_SCK); <span class="comment">// set SCK hi</span>00273 sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SCK); <span class="comment">// set SCK as output</span>00274 cbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MISO); <span class="comment">// set MISO as input</span>00275 sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_MOSI); <span class="comment">// set MOSI as output</span>00276 sbi(ENC28J60_SPI_DDR, ENC28J60_SPI_SS); <span class="comment">// SS must be output for Master mode to work</span>00277 <span class="comment">// initialize SPI interface</span>00278 <span class="comment">// master mode</span>00279 sbi(SPCR, MSTR);00280 <span class="comment">// select clock phase positive-going in middle of data</span>00281 cbi(SPCR, CPOL);00282 <span class="comment">// Data order MSB first</span>00283 cbi(SPCR,DORD);00284 <span class="comment">// switch to f/4 2X = f/2 bitrate</span>00285 cbi(SPCR, SPR0);00286 cbi(SPCR, SPR1);00287 sbi(SPSR, SPI2X);00288 <span class="comment">// enable SPI</span>00289 sbi(SPCR, SPE);00290 00291 <span class="comment">// perform system reset</span>00292 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);00293 <span class="comment">// check CLKRDY bit to see if reset is complete</span>00294 delay_us(50);00295 <span class="keywordflow">while</span>(!(<a class="code" href="group__enc28j60.html#ga5">enc28j60Read</a>(ESTAT) & ESTAT_CLKRDY));00296 00297 <span class="comment">// do bank 0 stuff</span>00298 <span class="comment">// initialize receive buffer</span>00299 <span class="comment">// 16-bit transfers, must write low byte first</span>00300 <span class="comment">// set receive buffer start address</span>00301 NextPacketPtr = RXSTART_INIT;00302 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTL, RXSTART_INIT&0xFF);00303 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXSTH, RXSTART_INIT>>8);00304 <span class="comment">// set receive pointer address</span>00305 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTL, RXSTART_INIT&0xFF);00306 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXRDPTH, RXSTART_INIT>>8);00307 <span class="comment">// set receive buffer end</span>00308 <span class="comment">// ERXND defaults to 0x1FFF (end of ram)</span>00309 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDL, RXSTOP_INIT&0xFF);00310 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ERXNDH, RXSTOP_INIT>>8);00311 <span class="comment">// set transmit buffer start</span>00312 <span class="comment">// ETXST defaults to 0x0000 (beginnging of ram)</span>00313 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTL, TXSTART_INIT&0xFF);00314 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(ETXSTH, TXSTART_INIT>>8);00315 00316 <span class="comment">// do bank 2 stuff</span>00317 <span class="comment">// enable MAC receive</span>00318 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);00319 <span class="comment">// bring MAC out of reset</span>00320 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MACON2, 0x00);00321 <span class="comment">// enable automatic padding and CRC operations</span>00322 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);00323 <span class="comment">// enc28j60Write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);</span>00324 <span class="comment">// set inter-frame gap (non-back-to-back)</span>00325 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGL, 0x12);00326 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAIPGH, 0x0C);00327 <span class="comment">// set inter-frame gap (back-to-back)</span>00328 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MABBIPG, 0x12);00329 <span class="comment">// Set the maximum packet size which the controller will accept</span>00330 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLL, MAX_FRAMELEN&0xFF); 00331 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAMXFLH, MAX_FRAMELEN>>8);00332 00333 <span class="comment">// do bank 3 stuff</span>00334 <span class="comment">// write MAC address</span>00335 <span class="comment">// NOTE: MAC address in ENC28J60 is byte-backward</span>00336 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR5, ENC28J60_MAC0);00337 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR4, ENC28J60_MAC1);00338 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR3, ENC28J60_MAC2);00339 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR2, ENC28J60_MAC3);00340 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR1, ENC28J60_MAC4);00341 <a class="code" href="group__enc28j60.html#ga6">enc28j60Write</a>(MAADR0, ENC28J60_MAC5);00342 00343 <span class="comment">// no loopback of transmitted frames</span>00344 <a class="code" href="group__enc28j60.html#ga8">enc28j60PhyWrite</a>(PHCON2, PHCON2_HDLDIS);00345 00346 <span class="comment">// switch to bank 0</span>00347 <a class="code" href="group__enc28j60.html#ga4">enc28j60SetBank</a>(ECON1);00348 <span class="comment">// enable interrutps</span>00349 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);00350 <span class="comment">// enable packet reception</span>00351 <a class="code" href="group__enc28j60.html#ga1">enc28j60WriteOp</a>(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);00352 <span class="comment">/*</span>00353 <span class="comment"> enc28j60PhyWrite(PHLCON, 0x0AA2);</span>00354 <span class="comment"></span>00355 <span class="comment"> // setup duplex ----------------------</span>00356 <span class="comment"></span>00357 <span class="comment"> // Disable receive logic and abort any packets currently being transmitted</span>00358 <span class="comment"> enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN);</span>00359 <span class="comment"> </span>00360 <span class="comment"> {</span>00361 <span class="comment"> u16 temp;</span>00362 <span class="comment"> // Set the PHY to the proper duplex mode</span>00363 <span class="comment"> temp = enc28j60PhyRead(PHCON1);</span>00364 <span class="comment"> temp &= ~PHCON1_PDPXMD;</span>00365 <span class="comment"> enc28j60PhyWrite(PHCON1, temp);</span>⌨️ 快捷键说明
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