2410init.s

英蓓特2410开发箱的软件包

	str	r1,[r0]
	
	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  @ all interrupt disable
	str	r1,[r0]

	ldr	r0,=INTSUBMSK
	ldr	r1,=0x7ff		@ all sub interrupt disable, 2002/04/10
	str	r1,[r0]

# To reduce PLL lock time, adjust the LOCKTIME register. 
	ldr	r0,=LOCKTIME
	ldr	r1,=0xffffff
	str	r1,[r0]
    
.ifdef PLL_ON_START
# Configure MPLL
	ldr	r0,=MPLLCON          
	ldr	r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)  @ Fin=12MHz,Fout=50MHz
	str	r1,[r0]
.endif

# Check if the boot is caused by the wake-up from POWER_OFF mode.
	ldr	r1,=GSTATUS2
	ldr	r0,[r1]
	tst	r0,#0x2
# In case of the wake-up from POWER_OFF mode, go to POWER_OFF_WAKEUP handler. 
	bne	WAKEUP_POWER_OFF

#=============================================================================================
# StartPointAfterPowerOffWakeUp  
#=============================================================================================
	.global StartPointAfterPowerOffWakeUp
StartPointAfterPowerOffWakeUp:
# Set memory control registers
#.equ	ROM_BASE,	0x0		/* image store address (in Flash)*/
    ldr	    r0,=SMRDATA
.ifdef	EXEC_FROM_RAM
    ldr		lr,=Image_RO_Base
	sub		r0,r0,lr
	ldr		lr,=ROM_BASE
	add		r0,r0,lr
.endif
	ldmia   r0,{r1-r13}
	ldr	    r0,=BWSCON  	/* BWSCON Address */
	stmia   r0,{r1-r13}

.ifdef	EXEC_FROM_RAM
	ldr r0,=ROM_BASE
	ldr r1,=Image_RO_Base
	ldr r3,=Image_ZI_Limit
LoopRw:
    cmp  	r1, r3
	ldrcc   r2, [r0], #4
	strcc  	r2, [r1], #4
	bcc   	LoopRw
		
	ldr 	pc,	=Jump
Jump:
	nop
	nop
	nop
.endif

# Initialize stacks
#	bl	InitStacks			@ if SVCstack is initialized before

#=============================================================================================
# InitStacks, initializing stacks of different mode
# Don't use DRAM operation, such as stmfd,ldmfd......
# 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
#=============================================================================================
InitStacks: 
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		@ UndefMode
	ldr	sp,=UndefStack
	
	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		@ AbortMode
	ldr	sp,=AbortStack

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		@ IRQMode
	ldr	sp,=IRQStack
    
	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		@ FIQMode
	ldr	sp,=FIQStack

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		@ SVCMode
	ldr	sp,=SVCStack
	
# USER mode has not be initialized.
#	mov	pc,lr 				@ The LR register won't be valid if the current mode is not SVC mode.

#  Setup IRQ handler
	ldr	r0,=HandleIRQ       @ This routine is needed
	ldr	r1,=IsrIRQ          @ if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
	str	r1,[r0]

# Copy and paste RW data/zero initialized data
	ldr	r0, = Image_RO_Limit@ Get pointer to ROM data
	ldr	r1, = Image_RW_Base	@ and RAM copy
	ldr	r3, = Image_ZI_Base   
	
# Zero init base => top of initialised data
	cmp	r0, r1				@ Check that they are different
	beq	F2
F1:       
	cmp	r1, r3				@ Copy init data
	ldrcc	r2, [r0], #4    @ --> LDRCC r2, [r0] + ADD r0, r0, #4         
	strcc	r2, [r1], #4    @ --> STRCC r2, [r1] + ADD r1, r1, #4
	bcc	F1
F2:       
	ldr	r1, = Image_ZI_Limit@ Top of zero init segment
	mov	r2, #0
B5:      
	cmp	r3, r1				@ Zero init
	strcc	r2, [r3], #4
	bcc	B5

	MRS	r0, CPSR
	BIC	r0, r0, #0x80		@ IRQ enable
	MSR	CPSR_cxsf, r0
	
/* jump to Main() */	
.ifdef THUMBCODE		@ for start-up code for Thumb mode
	orr	lr,pc,#1
	bx	lr
	.thumb
	bl	Main			@ Don't use main() because...
.else
	.arm
	bl	Main			@ Don't use main() because...
.endif
	b	.                       

#=============================================================================================
#SMRDATA
# Memory configuration should be optimized for best performance 
# The following parameter is not optimized.                     
# Memory access cycle parameter strategy
# 1) The memory settings is  safe parameters even at HCLK=75Mhz.
# 2) SDRAM refresh period is for HCLK=75Mhz. 
#=============================================================================================
	.ltorg
SMRDATA:
	.long (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
	.long ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   @ GCS0
	.long ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   @ GCS1 
	.long ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   @ GCS2
	.long ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   @ GCS3
	.long ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   @ GCS4
	.long ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   @ GCS5
	.long ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    @ GCS6
	.long ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    @ GCS7
	.long ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    

	.long 0x32            @ SCLK power saving mode, BANKSIZE 128M/128M
   	.long 0x30            @ MRSR6 CL=3clk
   	.long 0x30            @ MRSR7
#	.long 0x20            @ MRSR6 CL=2clk
#	.long 0x20            @ MRSR7

#=======================================================================================================================
# ARM core's exception and user interrupt handler store address 
# The address may be different between the different assemble after link.
#=============================================================================================
	.align
.equ	HandleReset,	_ISR_STARTADDRESS
.equ	HandleUndef,	_ISR_STARTADDRESS+4
.equ	HandleSWI,		_ISR_STARTADDRESS+4*2
.equ	HandlePabort,	_ISR_STARTADDRESS+4*3
.equ	HandleDabort,	_ISR_STARTADDRESS+4*4
.equ	HandleReserved,	_ISR_STARTADDRESS+4*5
.equ	HandleIRQ,		_ISR_STARTADDRESS+4*6
.equ	HandleFIQ,		_ISR_STARTADDRESS+4*7

#Don't use the label 'IntVectorTable',
#The value of IntVectorTable is different with the address you think it may be.
#IntVectorTable
.equ	HandleEINT0,    _ISR_STARTADDRESS+4*8
.equ	HandleEINT1,	_ISR_STARTADDRESS+4*9
.equ	HandleEINT2, 	_ISR_STARTADDRESS+4*10
.equ	HandleEINT3,	_ISR_STARTADDRESS+4*11
.equ	HandleEINT4_7,	_ISR_STARTADDRESS+4*12
.equ	HandleEINT8_23,	_ISR_STARTADDRESS+4*13
.equ	HandleRSV6,		_ISR_STARTADDRESS+4*14
.equ	HandleBATFLT,	_ISR_STARTADDRESS+4*15
.equ	HandleTICK,		_ISR_STARTADDRESS+4*16
.equ	HandleWDT,		_ISR_STARTADDRESS+4*17
.equ	HandleTIMER0,	_ISR_STARTADDRESS+4*18
.equ	HandleTIMER1,	_ISR_STARTADDRESS+4*19
.equ	HandleTIMER2, 	_ISR_STARTADDRESS+4*20
.equ	HandleTIMER3, 	_ISR_STARTADDRESS+4*21
.equ	HandleTIMER4, 	_ISR_STARTADDRESS+4*22
.equ	HandleUART2, 	_ISR_STARTADDRESS+4*23
.equ	HandleLCD,		_ISR_STARTADDRESS+4*24
.equ	HandleDMA0,		_ISR_STARTADDRESS+4*25
.equ	HandleDMA1,		_ISR_STARTADDRESS+4*26
.equ	HandleDMA2,		_ISR_STARTADDRESS+4*27
.equ	HandleDMA3,		_ISR_STARTADDRESS+4*28
.equ	HandleMMC,		_ISR_STARTADDRESS+4*29
.equ	HandleSPI0,		_ISR_STARTADDRESS+4*30
.equ	HandleUART1,	_ISR_STARTADDRESS+4*31
.equ	HandleRSV24,	_ISR_STARTADDRESS+4*32
.equ	HandleUSBD,		_ISR_STARTADDRESS+4*33	
.equ	HandleUSBH,     _ISR_STARTADDRESS+4*34	
.equ	HandleIIC,		_ISR_STARTADDRESS+4*35  	
.equ	HandleUART,     _ISR_STARTADDRESS+4*36 	
.equ	HandleSPI1,     _ISR_STARTADDRESS+4*37 	
.equ	HandleRTC,		_ISR_STARTADDRESS+4*38
.equ	HandleADC,		_ISR_STARTADDRESS+4*39
.end