tvp7000.c

TI公司主流的A/D转换芯片tvp7000的驱动程序（基于6446平台）

/*
 *  Copyright(C) 2006-2008 Neuros Technology International LLC.
 *               <www.neurostechnology.com>
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, version 2 of the License.
 *
 *  This program is distributed in the hope that, in addition to its
 *  original purpose to support Neuros hardware, it will be useful
 *  otherwise, but WITHOUT ANY WARRANTY; without even the implied
 *  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *  See the GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 ****************************************************************************
 *
 * tvp7000 driver.
 *
 */

#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <media/tvp7000.h>
#include <media/v4l2-common.h>
#include <media/davinci_vpfe.h>
#include <asm/arch/gpio.h>

#define DEBUG
#ifdef DEBUG
#define DPRINTK(x...)  do { \
                printk(KERN_INFO "<%s>: ", __FUNCTION__); printk(x); \
        } while (0)

#define FN_IN  printk(KERN_INFO "<%s> start:\n", __FUNCTION__)

#else
#define DPRINTK(x...)
#define FN_IN

#endif

#define HD_CAP_GPIO             GPIO(39)
#define NUM_OF_REGS(x) \
        (sizeof(x) / sizeof(*x))
#define STD(x)  \
    ((x) < TOTAL_STANDARD ? video_std + (x) : NULL)
#define TVP7000_I2C_RETRY 3
#define INIT_DEFAULT 0

/* I2C Addresses to scan */
static unsigned short normal_i2c[] = {
        0xB8 >> 1,
        0xB9 >> 1,
        I2C_CLIENT_END};

/* This makes all addr_data:s */
I2C_CLIENT_INSMOD;

static struct i2c_client *tvp7000_client;

MODULE_DESCRIPTION("Texas Instruments TVP7000 video decoder driver");
MODULE_AUTHOR("Neuros Technology LLC");
MODULE_LICENSE("GPL");

struct i2c_reg_value
{
        u8 reg;
        u8 value;
};

static const struct i2c_reg_value tvp7000_init_component[] = {
        { /* 0x01 */
                TVP7000_PLL_DIVIDE_MSB, 0x6b
        },
        { /* 0x02 */
                TVP7000_PLL_DIVIDE_LSB, 0x40
        },
        { /* 0x03 */
                TVP7000_PLL_CTRL, 0x68
        },
        { /* 0x04 */
                TVP7000_PHASE_SELECT, 0xb1
        },
        { /* 0x05 */
                TVP7000_CLAMP_START, 0x06
        },
        { /* 0x06 */
                TVP7000_CLAMP_WIDTH, 0x10
        },
        { /* 0x07 */
                TVP7000_HSYNC_OUTPUT_WIDTH, 0x60
        },
        { /* 0x08 */
                TVP7000_BLUE_FINE_GAIN, 0x80
        },
        { /* 0x09 */
                TVP7000_GREEN_FINE_GAIN, 0x80
        },
        { /* 0x0A */
                TVP7000_RED_FINE_GAIN, 0x80
        },
        { /* 0x0B */
                TVP7000_BLUE_FINE_OFFSET, 0x80
        },
        { /* 0x0C */
                TVP7000_GREEN_FINE_OFFSET, 0x80
        },
        { /* 0x0D */
                TVP7000_RED_FINE_OFFSET, 0x80
        },
        { /* 0x0E */
                TVP7000_SYNC_CTRL_1, 0x20
        },
        { /* 0x0F */
                TVP7000_PLL_CLAMP_CTRL, 0x2E
        },
        { /* 0x10 */
                TVP7000_SYNC_ON_GREEN, 0x85
        },
        { /* 0x11 */
                TVP7000_SYNC_SEPARATOR, 0x47
        },
        { /* 0x12 */
                TVP7000_PRE_COAST, 0x03
        },
        { /* 0x13 */
                TVP7000_POST_COAST, 0x0c
        },
        { /* 0x15 */
                TVP7000_OUTPUT_FORMATTER, 0x02
        },
        { /* 0x16 */
                TVP7000_TEST_REG, 0xe5
        },
        { /* 0x19 */
                TVP7000_INPUT_MUX_1, 0x00
        },
        { /* 0x1A */
                TVP7000_INPUT_MUX_2, 0x85
        },
        { /* 0x1B */
                TVP7000_BLUE_GREEN_GAIN, 0x55
        },
        { /* 0x1C */
                TVP7000_RED_COARSE_GAIN, 0x05
        },
        { /* 0x1D */
                TVP7000_FINE_OFFSET_LSB, 0x00
        },
        { /* 0x1E */
                TVP7000_BLUE_COARSE_OFFSET, 0x1f
        },
        { /* 0x1F */
                TVP7000_GREEN_COARSE_OFFSET, 0x1f
        },
        { /* 0x20 */
                TVP7000_RED_COARSE_OFFSET, 0x1f
        },
        { /* 0x21 */
                TVP7000_HSOUT_OUTPUT_START, 0x08
        },
        { /* 0x22 */
                TVP7000_MISC_CTRL, 0x08
        },
        { /* 0x26 */
                TVP7000_AUTO_CTRL_ENABLE, 0x80
        },
        { /* 0x28 */
                TVP7000_AUTO_CTRL_FILTER, 0x03
        },
        { /* 0x2A */
                TVP7000_FINE_CLAMP_CTRL, 0x07
        },
        { /* 0x2B */
                TVP7000_POWER_CTRL, 0x00
        },
        { /* 0x2C */
                TVP7000_ADC_SETUP, 0x50
        },
        { /* 0x2D */
                TVP7000_COARSE_CLAMP_CTRL_1, 0x00
        },
        { /* 0x2E */
                TVP7000_SOG_CLAMP, 0x80
        },
        { /* 0x31 */
                TVP7000_ALC_PLACEMENT, 0x18
        },
};

#if INIT_DEFAULT
static const struct i2c_reg_value tvp7000_init_default[] = {
        { /* 0x01 */
                TVP7000_PLL_DIVIDE_MSB, 0x69
        },
        { /* 0x02 */
                TVP7000_PLL_DIVIDE_LSB, 0xD0
        },
        { /* 0x03 */
                TVP7000_PLL_CTRL, 0x48
        },
        { /* 0x04 */
                TVP7000_PHASE_SELECT, 0x80
        },
        { /* 0x05 */
                TVP7000_CLAMP_START, 0x80
        },
        { /* 0x06 */
                TVP7000_CLAMP_WIDTH, 0x80
        },
        { /* 0x07 */
                TVP7000_HSYNC_OUTPUT_WIDTH, 0x20
        },
        { /* 0x08 */
                TVP7000_BLUE_FINE_GAIN, 0x80
        },
        { /* 0x09 */
                TVP7000_GREEN_FINE_GAIN, 0x80
        },
        { /* 0x0A */
                TVP7000_RED_FINE_GAIN, 0x80
        },
        { /* 0x0B */
                TVP7000_BLUE_FINE_OFFSET, 0x80
        },
        { /* 0x0C */
                TVP7000_GREEN_FINE_OFFSET, 0x80
        },
        { /* 0x0D */
                TVP7000_RED_FINE_OFFSET, 0x80
        },
        { /* 0x0E */
                TVP7000_SYNC_CTRL_1, 0x40
        },
        { /* 0x0F */
                TVP7000_PLL_CLAMP_CTRL, 0x4E
        },
        { /* 0x10 */
                TVP7000_SYNC_ON_GREEN, 0xB8
        },
        { /* 0x11 */
                TVP7000_SYNC_SEPARATOR, 0x20
        },
        { /* 0x12 */
                TVP7000_PRE_COAST, 0x00
        },
        { /* 0x13 */
                TVP7000_POST_COAST, 0x00
        },
        { /* 0x15 */
                TVP7000_OUTPUT_FORMATTER, 0x00
        },
        { /* 0x16 */
                TVP7000_TEST_REG, 0x00
        },
        { /* 0x19 */
                TVP7000_INPUT_MUX_1, 0x00
        },
        { /* 0x1A */
                TVP7000_INPUT_MUX_2, 0x00
        },
        { /* 0x1B */
                TVP7000_BLUE_GREEN_GAIN, 0x55
        },
        { /* 0x1C */
                TVP7000_RED_COARSE_GAIN, 0x05
        },
        { /* 0x1D */
                TVP7000_FINE_OFFSET_LSB, 0x00
        },
        { /* 0x1E */
                TVP7000_BLUE_COARSE_OFFSET, 0x20
        },
        { /* 0x1F */
                TVP7000_GREEN_COARSE_OFFSET, 0x20
        },
        { /* 0x20 */
                TVP7000_RED_COARSE_OFFSET, 0x20
        },
        { /* 0x21 */
                TVP7000_HSOUT_OUTPUT_START, 0x09
        },
        { /* 0x22 */
                TVP7000_MISC_CTRL, 0x00
        },
        { /* 0x26 */
                TVP7000_AUTO_CTRL_ENABLE, 0x00
        },
        { /* 0x28 */
                TVP7000_AUTO_CTRL_FILTER, 0x00
        },
        { /* 0x2A */
                TVP7000_FINE_CLAMP_CTRL, 0x00
        },
        { /* 0x2B */
                TVP7000_POWER_CTRL, 0x00
        },
        { /* 0x2C */
                TVP7000_ADC_SETUP, 0x00
        },
        { /* 0x2D */
                TVP7000_COARSE_CLAMP_CTRL_1, 0x00
        },
        { /* 0x2E */
                TVP7000_SOG_CLAMP, 0x00
        },
        { /* 0x31 */
                TVP7000_ALC_PLACEMENT, 0x00
        },
};
#endif

struct tvp7000_video_std
{
        u8 plldiv_msb;
        u8 plldiv_lsb;
        u8 pll_ctrl;
        u8 phase_select_bit0;
        u8 pre_coast;
        u8 post_coast;
        u8 clamp_start;
        u8 clamp_width;
        u8 alc_placement;
};

static const struct tvp7000_video_std video_std[] = {
        { /* VGA standard: 640*480 resolution,60HZ refresh rate,
                        31.5kHZ Horizontal frequency,25.175MHZ pixel rate,
                */
                .plldiv_msb = 0x64,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x01,
        },
        { /* VGA standard: 640*480 resolution,72HZ refresh rate,
                        37.9kHZ Horizontal frequency,31.5MHZ pixel rate,
                */
                .plldiv_msb = 0x68,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x58,
                .phase_select_bit0 = 0x01,
        },
        { /* VGA standard: 640*480 resolution,75HZ refresh rate,
                        37.5kHZ Horizontal frequency,31.5MHZ pixel rate,
                */
                .plldiv_msb = 0x69,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x58,
                .phase_select_bit0 = 0x01,
        },
        { /* VGA standard: 640*480 resolution,85HZ refresh rate,
                        43.3kHZ Horizontal frequency,36MHZ pixel rate,
                */
                .plldiv_msb = 0x34,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* SVGA standard: 800*600 resolution,56HZ refresh rate,
                        35.1kHZ Horizontal frequency,36MHZ pixel rate,
                */
                .plldiv_msb = 0x40,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* SVGA standard: 800*600 resolution,60HZ refresh rate,
                        37.9kHZ Horizontal frequency,40MHZ pixel rate,
                */
                .plldiv_msb = 0x42,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* SVGA standard: 800*600 resolution,72HZ refresh rate,
                        48.1kHZ Horizontal frequency,50MHZ pixel rate,
                */
                .plldiv_msb = 0x41,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* SVGA standard: 800*600 resolution,75HZ refresh rate,
                        46.9kHZ Horizontal frequency,49.5MHZ pixel rate,
                */
                .plldiv_msb = 0x42,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* SVGA standard: 800*600 resolution,85HZ refresh rate,
                        53.7kHZ Horizontal frequency,56.25MHZ pixel rate,
                */
                .plldiv_msb = 0x41,
                .plldiv_lsb = 0x80,
                .pll_ctrl = 0x68,
                .phase_select_bit0 = 0x00,
        },
        { /* XGA standard: 1024*768 resolution,60HZ refresh rate,
                        48.4kHZ Horizontal frequency,65MHZ pixel rate,
                */
                .plldiv_msb = 0x54,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0x58,
                .phase_select_bit0 = 0x00,
        },
        { /* XGA standard: 1024*768 resolution,70HZ refresh rate,
                        56.5kHZ Horizontal frequency,75MHZ pixel rate,
                */
                .plldiv_msb = 0x53,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0xA8,
                .phase_select_bit0 = 0x00,
        },
        { /* XGA standard: 1024*768 resolution,75HZ refresh rate,
                        60kHZ Horizontal frequency,78.75MHZ pixel rate,
                */
                .plldiv_msb = 0x52,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0xA8,
                .phase_select_bit0 = 0x00,
        },
        { /* XGA standard: 1024*768 resolution,85HZ refresh rate,
                        68.7kHZ Horizontal frequency,94.5MHZ pixel rate,
                */
                .plldiv_msb = 0x56,
                .plldiv_lsb = 0x00,
                .pll_ctrl = 0xA8,
                .phase_select_bit0 = 0x00,
        },
        { /* SXGA standard: 1280*1024 resolution,60HZ refresh rate,
                        64kHZ Horizontal frequency,108MHZ pixel rate,
                */
                .plldiv_msb = 0x69,
                .plldiv_lsb = 0x80,
                .pll_ctrl = 0xA8,
                .phase_select_bit0 = 0x00,
        },
        { /* SXGA standard: 1280*1024 resolution,75HZ refresh rate,
                        80kHZ Horizontal frequency,135MHZ pixel rate,
                */
                .plldiv_msb = 0x69,
                .plldiv_lsb = 0x80,
                .pll_ctrl = 0x98,
                .phase_select_bit0 = 0x00,
        },