clgenfb.c

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

		case BT_SPECTRUM:
		case BT_PICASSO4:
		case BT_ALPINE:
		case BT_GD5480:
			DPRINTK (" (for GD54xx)\n");
			vga_wseq (fb_info->regs, CL_SEQR7,
				  _par->multiplexing ?
				  	bi->sr07_8bpp_mux : bi->sr07_8bpp);
			break;

		case BT_LAGUNA:
			DPRINTK (" (for GD546x)\n");
			vga_wseq (fb_info->regs, CL_SEQR7,
				vga_rseq (fb_info->regs, CL_SEQR7) | 0x01);
			break;

		default:
			printk (KERN_WARNING "clgen: unknown Board\n");
			break;
		}

		switch (fb_info->btype) {
		case BT_SD64:
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x1d);		/* MCLK select */
			break;

		case BT_PICCOLO:
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* ### vorher 1c MCLK select */
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			break;

		case BT_PICASSO:
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* ### vorher 1c MCLK select */
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			break;

		case BT_SPECTRUM:
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* ### vorher 1c MCLK select */
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			break;

		case BT_PICASSO4:
#ifdef CONFIG_ZORRO
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb8);	/* ### INCOMPLETE!! */
#endif
/*          vga_wseq (fb_info->regs, CL_SEQR1F, 0x1c); */
			break;

		case BT_ALPINE:
			DPRINTK (" (for GD543x)\n");
			clgen_set_mclk (fb_info, _par->mclk, _par->divMCLK);
			/* We already set SRF and SR1F */
			break;

		case BT_GD5480:
		case BT_LAGUNA:
			DPRINTK (" (for GD54xx)\n");
			/* do nothing */
			break;

		default:
			printk (KERN_WARNING "clgen: unknown Board\n");
			break;
		}

		vga_wgfx (fb_info->regs, VGA_GFX_MODE, 64);	/* mode register: 256 color mode */
		WGen (fb_info, VGA_PEL_MSK, 0xff);	/* pixel mask: pass-through all planes */
		if (_par->multiplexing)
			WHDR (fb_info, 0x4a);	/* hidden dac reg: 1280x1024 */
		else
			WHDR (fb_info, 0);	/* hidden dac: nothing */
		vga_wseq (fb_info->regs, VGA_SEQ_MEMORY_MODE, 0x0a);	/* memory mode: chain4, ext. memory */
		vga_wseq (fb_info->regs, VGA_SEQ_PLANE_WRITE, 0xff);	/* plane mask: enable writing to all 4 planes */
		offset = _par->var.xres_virtual / 8;
	}

	/******************************************************
	 *
	 * 16 bpp
	 *
	 */

	else if (_par->var.bits_per_pixel == 16) {
		DPRINTK ("clgen: preparing for 16 bit deep display\n");
		switch (fb_info->btype) {
		case BT_SD64:
			vga_wseq (fb_info->regs, CL_SEQR7, 0xf7);	/* Extended Sequencer Mode: 256c col. mode */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x1e);		/* MCLK select */
			break;

		case BT_PICCOLO:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x87);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_PICASSO:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x27);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_SPECTRUM:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x87);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_PICASSO4:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x27);
/*          vga_wseq (fb_info->regs, CL_SEQR1F, 0x1c);  */
			break;

		case BT_ALPINE:
			DPRINTK (" (for GD543x)\n");
			if (IS_7548(fb_info)) {
				vga_wseq (fb_info->regs, CL_SEQR7, 
					  (vga_rseq (fb_info->regs, CL_SEQR7) & 0xE0)
					  | 0x17);
				WHDR (fb_info, 0xC1);
			} else {
				if (_par->HorizRes >= 1024)
					vga_wseq (fb_info->regs, CL_SEQR7, 0xa7);
				else
					vga_wseq (fb_info->regs, CL_SEQR7, 0xa3);
			}	
			clgen_set_mclk (fb_info, _par->mclk, _par->divMCLK);
			break;

		case BT_GD5480:
			DPRINTK (" (for GD5480)\n");
			vga_wseq (fb_info->regs, CL_SEQR7, 0x17);
			/* We already set SRF and SR1F */
			break;

		case BT_LAGUNA:
			DPRINTK (" (for GD546x)\n");
			vga_wseq (fb_info->regs, CL_SEQR7,
				vga_rseq (fb_info->regs, CL_SEQR7) & ~0x01);
			break;

		default:
			printk (KERN_WARNING "CLGEN: unknown Board\n");
			break;
		}

		vga_wgfx (fb_info->regs, VGA_GFX_MODE, 64);	/* mode register: 256 color mode */
		WGen (fb_info, VGA_PEL_MSK, 0xff);	/* pixel mask: pass-through all planes */
#ifdef CONFIG_PCI
		WHDR (fb_info, 0xc0);	/* Copy Xbh */
#elif defined(CONFIG_ZORRO)
		/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
		WHDR (fb_info, 0xa0);	/* hidden dac reg: nothing special */
#endif
		vga_wseq (fb_info->regs, VGA_SEQ_MEMORY_MODE, 0x0a);	/* memory mode: chain4, ext. memory */
		vga_wseq (fb_info->regs, VGA_SEQ_PLANE_WRITE, 0xff);	/* plane mask: enable writing to all 4 planes */
		offset = _par->var.xres_virtual / 4;
	}

	/******************************************************
	 *
	 * 32 bpp
	 *
	 */

	else if (_par->var.bits_per_pixel == 32) {
		DPRINTK ("clgen: preparing for 24/32 bit deep display\n");
		switch (fb_info->btype) {
		case BT_SD64:
			vga_wseq (fb_info->regs, CL_SEQR7, 0xf9);	/* Extended Sequencer Mode: 256c col. mode */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x1e);		/* MCLK select */
			break;

		case BT_PICCOLO:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x85);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_PICASSO:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x25);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_SPECTRUM:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x85);
			vga_wseq (fb_info->regs, CL_SEQRF, 0xb0);	/* Fast Page-Mode writes */
			vga_wseq (fb_info->regs, CL_SEQR1F, 0x22);		/* MCLK select */
			break;

		case BT_PICASSO4:
			vga_wseq (fb_info->regs, CL_SEQR7, 0x25);
/*          vga_wseq (fb_info->regs, CL_SEQR1F, 0x1c);  */
			break;

		case BT_ALPINE:
			DPRINTK (" (for GD543x)\n");
			vga_wseq (fb_info->regs, CL_SEQR7, 0xa9);
			clgen_set_mclk (fb_info, _par->mclk, _par->divMCLK);
			break;

		case BT_GD5480:
			DPRINTK (" (for GD5480)\n");
			vga_wseq (fb_info->regs, CL_SEQR7, 0x19);
			/* We already set SRF and SR1F */
			break;

		case BT_LAGUNA:
			DPRINTK (" (for GD546x)\n");
			vga_wseq (fb_info->regs, CL_SEQR7,
				vga_rseq (fb_info->regs, CL_SEQR7) & ~0x01);
			break;

		default:
			printk (KERN_WARNING "clgen: unknown Board\n");
			break;
		}

		vga_wgfx (fb_info->regs, VGA_GFX_MODE, 64);	/* mode register: 256 color mode */
		WGen (fb_info, VGA_PEL_MSK, 0xff);	/* pixel mask: pass-through all planes */
		WHDR (fb_info, 0xc5);	/* hidden dac reg: 8-8-8 mode (24 or 32) */
		vga_wseq (fb_info->regs, VGA_SEQ_MEMORY_MODE, 0x0a);	/* memory mode: chain4, ext. memory */
		vga_wseq (fb_info->regs, VGA_SEQ_PLANE_WRITE, 0xff);	/* plane mask: enable writing to all 4 planes */
		offset = _par->var.xres_virtual / 4;
	}

	/******************************************************
	 *
	 * unknown/unsupported bpp
	 *
	 */

	else {
		printk (KERN_ERR "clgen: What's this?? requested color depth == %d.\n",
			_par->var.bits_per_pixel);
	}

	if (IS_7548(fb_info)) {
		vga_wseq (fb_info->regs, CL_SEQR2D, 
			vga_rseq (fb_info->regs, CL_SEQR2D) | 0xC0);
	}

	vga_wcrt (fb_info->regs, VGA_CRTC_OFFSET, offset & 0xff);
	tmp = 0x22;
	if (offset & 0x100)
		tmp |= 0x10;	/* offset overflow bit */

	vga_wcrt (fb_info->regs, CL_CRT1B, tmp);	/* screen start addr #16-18, fastpagemode cycles */

	if (fb_info->btype == BT_SD64 ||
	    fb_info->btype == BT_PICASSO4 ||
	    fb_info->btype == BT_ALPINE ||
	    fb_info->btype == BT_GD5480)
		vga_wcrt (fb_info->regs, CL_CRT1D, 0x00);	/* screen start address bit 19 */

	vga_wcrt (fb_info->regs, VGA_CRTC_CURSOR_HI, 0);	/* text cursor location high */
	vga_wcrt (fb_info->regs, VGA_CRTC_CURSOR_LO, 0);	/* text cursor location low */
	vga_wcrt (fb_info->regs, VGA_CRTC_UNDERLINE, 0);	/* underline row scanline = at very bottom */

	vga_wattr (fb_info->regs, VGA_ATC_MODE, 1);	/* controller mode */
	vga_wattr (fb_info->regs, VGA_ATC_OVERSCAN, 0);		/* overscan (border) color */
	vga_wattr (fb_info->regs, VGA_ATC_PLANE_ENABLE, 15);	/* color plane enable */
	vga_wattr (fb_info->regs, CL_AR33, 0);	/* pixel panning */
	vga_wattr (fb_info->regs, VGA_ATC_COLOR_PAGE, 0);	/* color select */

	/* [ EGS: SetOffset(); ] */
	/* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
	AttrOn (fb_info);

	vga_wgfx (fb_info->regs, VGA_GFX_SR_VALUE, 0);	/* set/reset register */
	vga_wgfx (fb_info->regs, VGA_GFX_SR_ENABLE, 0);		/* set/reset enable */
	vga_wgfx (fb_info->regs, VGA_GFX_COMPARE_VALUE, 0);	/* color compare */
	vga_wgfx (fb_info->regs, VGA_GFX_DATA_ROTATE, 0);	/* data rotate */
	vga_wgfx (fb_info->regs, VGA_GFX_PLANE_READ, 0);	/* read map select */
	vga_wgfx (fb_info->regs, VGA_GFX_MISC, 1);	/* miscellaneous register */
	vga_wgfx (fb_info->regs, VGA_GFX_COMPARE_MASK, 15);	/* color don't care */
	vga_wgfx (fb_info->regs, VGA_GFX_BIT_MASK, 255);	/* bit mask */

	vga_wseq (fb_info->regs, CL_SEQR12, 0x0);	/* graphics cursor attributes: nothing special */

	/* finally, turn on everything - turn off "FullBandwidth" bit */
	/* also, set "DotClock%2" bit where requested */
	tmp = 0x01;

/*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
    if (var->vmode & FB_VMODE_CLOCK_HALVE)
	tmp |= 0x08;
*/

	vga_wseq (fb_info->regs, VGA_SEQ_CLOCK_MODE, tmp);
	DPRINTK ("CL_SEQR1: %d\n", tmp);

	fb_info->currentmode = *_par;

	DPRINTK ("virtual offset: (%d,%d)\n", _par->var.xoffset, _par->var.yoffset);
	/* pan to requested offset */
	clgen_pan_display (&fb_info->currentmode.var, (struct fb_info_gen *) fb_info);

#ifdef CLGEN_DEBUG
	clgen_dump ();
#endif

	DPRINTK ("EXIT\n");
	return;
}


static int clgen_getcolreg (unsigned regno, unsigned *red, unsigned *green,
			    unsigned *blue, unsigned *transp,
			    struct fb_info *info)
{
    struct clgenfb_info *fb_info = (struct clgenfb_info *)info;

    if (regno > 255)
	return 1;
    *red = fb_info->palette[regno].red;
    *green = fb_info->palette[regno].green;
    *blue = fb_info->palette[regno].blue;
    *transp = 0;
    return 0;
}


static int clgen_setcolreg (unsigned regno, unsigned red, unsigned green,
			    unsigned blue, unsigned transp,
			    struct fb_info *info)
{
	struct clgenfb_info *fb_info = (struct clgenfb_info *) info;

	if (regno > 255)
		return -EINVAL;

#ifdef FBCON_HAS_CFB8
	switch (fb_info->currentmode.var.bits_per_pixel) {
	case 8:
		/* "transparent" stuff is completely ignored. */
		WClut (fb_info, regno, red >> 10, green >> 10, blue >> 10);
		break;
	default:
		/* do nothing */
		break;
	}
#endif	/* FBCON_HAS_CFB8 */

	fb_info->palette[regno].red = red;
	fb_info->palette[regno].green = green;
	fb_info->palette[regno].blue = blue;

	if (regno >= 16)
		return 0;

	switch (fb_info->currentmode.var.bits_per_pixel) {

#ifdef FBCON_HAS_CFB16
	case 16:
		assert (regno < 16);
		if(isPReP) {
			fb_info->fbcon_cmap.cfb16[regno] =
			    ((red & 0xf800) >> 9) |
			    ((green & 0xf800) >> 14) |
			    ((green & 0xf800) << 2) |
			    ((blue & 0xf800) >> 3);
		} else {
			fb_info->fbcon_cmap.cfb16[regno] =
			    ((red & 0xf800) >> 1) |
			    ((green & 0xf800) >> 6) |
			    ((blue & 0xf800) >> 11);
		}
#endif /* FBCON_HAS_CFB16 */

#ifdef FBCON_HAS_CFB24
	case 24:
		assert (regno < 16);
		fb_info->fbcon_cmap.cfb24[regno] =
			(red   << fb_info->currentmode.var.red.offset)   |
			(green << fb_info->currentmode.var.green.offset) |
			(blue  << fb_info->currentmode.var.blue.offset);
		break;
#endif /* FBCON_HAS_CFB24 */

#ifdef FBCON_HAS_CFB32
	case 32:
		assert (regno < 16);
		if(isPReP) {
			fb_info->fbcon_cmap.cfb32[regno] =
			    ((red & 0xff00)) |
			    ((green & 0xff00) << 8) |
			    ((blue & 0xff00) << 16);
		} else {
			fb_info->fbcon_cmap.cfb32[regno] =
			    ((red & 0xff00) << 8) |
			    ((green & 0xff00)) |
			    ((blue & 0xff00) >> 8);
		}
		break;
#endif /* FBCON_HAS_CFB32 */
	default:
		/* do nothing */
		break;
	}

	return 0;
}

/*************************************************************************
	clgen_pan_display()

	performs display panning - provided hardware permits this
**************************************************************************/
static int clgen_pan_display (const struct fb_var_screeninfo *var,
			      struct fb_info_gen *info)
{
	int xoffset = 0;
	int yoffset = 0;
	unsigned long base;
	unsigned char tmp = 0, tmp2 = 0, xpix;
	struct clgenfb_info *fb_info = (struct clgenfb_info *) info;

	DPRINTK ("ENTER\n");

	/* no range checks for xoffset and yoffset,   */
	/* as fbgen_pan_display has already done this */

	fb_info->currentmode.var.xoffset = var->xoffset;
	fb_info->currentmode.var.yoffset = var->yoffset;

	xoffset = var->xoffset * fb_info->currentmode.var.bits_per_pixel / 8;
	yoffset = var->yoffset;

	base = yoffset * fb_info->currentmode.line_length + xoffset;

	if (fb_info->currentmode.var.bits_per_pixel == 1) {
		/* base is already correct */
		xpix = (unsigned char) (var->xoffset % 8);
	} else {
		base /= 4;
		xpix = (unsigned char) ((xoffset % 4) * 2);
	}

	/* lower 8 + 8 bits of screen start address */
	vga_wcrt (fb_info->regs, VGA_CRTC_START_LO, (unsigned char) (base & 0xff));
	vga_wcrt (fb_info->regs, VGA_CRTC_START_HI, (unsigned char) (base >> 8));

	/* construct bits 16, 17 and 18 of screen start address */
	if (base & 0x10000)
		tmp |= 0x01;
	if (base & 0x20000)
		tmp |= 0x04;
	if (base & 0x40000)
		tmp |= 0x08;

	tmp2 = (vga_rcrt (fb_info->regs, CL_CRT1B) & 0xf2) | tmp;	/* 0xf2 is %11110010, exclude tmp bits */
	vga_wcrt (fb_info->regs, CL_CRT1B, tmp2);

	/* construct bit 19 of screen start address */
	if (clgen_board_info[fb_info->btype].scrn_start_bit19) {
		tmp2 = 0;