tgafb.c

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

    TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR0_REG);
    TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR1_REG);

    /* init video timing regs */
    TGA_WRITE_REG(par->htimings, TGA_HORIZ_REG);
    TGA_WRITE_REG(par->vtimings, TGA_VERT_REG);

    /* initalise RAMDAC */
    if (fb_info.tga_type == TGA_TYPE_8PLANE) { 

	/* init BT485 RAMDAC registers */
	BT485_WRITE(0xa2 | (par->sync_on_green ? 0x8 : 0x0), BT485_CMD_0);
	BT485_WRITE(0x01, BT485_ADDR_PAL_WRITE);
	BT485_WRITE(0x14, BT485_CMD_3); /* cursor 64x64 */
	BT485_WRITE(0x40, BT485_CMD_1);
	BT485_WRITE(0x20, BT485_CMD_2); /* cursor off, for now */
	BT485_WRITE(0xff, BT485_PIXEL_MASK);

	/* fill palette registers */
	BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE);
	TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);

	for (i = 0; i < 16; i++) {
	    j = color_table[i];
	    TGA_WRITE_REG(default_red[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(default_grn[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(default_blu[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    palette[i].red=default_red[j];
	    palette[i].green=default_grn[j];
	    palette[i].blue=default_blu[j];
	}
	for (i = 0; i < 240*3; i += 4) {
	    TGA_WRITE_REG(0x55|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG);
	}	  

    } else { /* 24-plane or 24plusZ */

	/* init BT463 registers */
	BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
	BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
	BT463_WRITE(BT463_REG_ACC, BT463_CMD_REG_2, 
		(par->sync_on_green ? 0x80 : 0x40));

	BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
	BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
	BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
	BT463_WRITE(BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);

	BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
	BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
	BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
	BT463_WRITE(BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);

	/* fill the palette */
	BT463_LOAD_ADDR(0x0000);
	TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG);

	for (i = 0; i < 16; i++) {
	    j = color_table[i];
	    TGA_WRITE_REG(default_red[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(default_grn[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(default_blu[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	}
	for (i = 0; i < 512*3; i += 4) {
	    TGA_WRITE_REG(0x55|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	}	  

	/* fill window type table after start of vertical retrace */
	while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01))
	    continue;
	TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG);
	mb();
	while (!(TGA_READ_REG(TGA_INTR_STAT_REG) & 0x01))
	    continue;
	TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG);

	BT463_LOAD_ADDR(BT463_WINDOW_TYPE_BASE);
	TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG);
	
	for (i = 0; i < 16; i++) {
	    TGA_WRITE_REG(0x00|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x01|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
	    TGA_WRITE_REG(0x80|(BT463_REG_ACC<<10), TGA_RAMDAC_REG);
	}
   
    }

    /* finally, enable video scan
	(and pray for the monitor... :-) */
    TGA_WRITE_REG(TGA_VALID_VIDEO, TGA_VALID_REG);
}


#define DIFFCHECK(x) { if( m <= 0x3f ) { \
      int delta = f - (TGA_PLL_BASE_FREQ * (x)) / (r << shift); \
      if (delta < 0) delta = -delta; \
      if (delta < min_diff) min_diff = delta, vm = m, va = a, vr = r; } }

static void tgafb_set_pll(int f)
{
    int                 n, shift, base, min_diff, target;
    int                 r,a,m,vm = 34, va = 1, vr = 30;

    for( r = 0 ; r < 12 ; r++ )
	TGA_WRITE_REG(!r, TGA_CLOCK_REG);

    if (f > TGA_PLL_MAX_FREQ)
	f = TGA_PLL_MAX_FREQ;

    if (f >= TGA_PLL_MAX_FREQ / 2)
	shift = 0;
    else if (f >= TGA_PLL_MAX_FREQ / 4)
	shift = 1;
    else
	shift = 2;

    TGA_WRITE_REG(shift & 1, TGA_CLOCK_REG);
    TGA_WRITE_REG(shift >> 1, TGA_CLOCK_REG);

    for( r = 0 ; r < 10 ; r++ ) {
	TGA_WRITE_REG(0, TGA_CLOCK_REG);
    }

    if (f <= 120000) {
	TGA_WRITE_REG(0, TGA_CLOCK_REG);
	TGA_WRITE_REG(0, TGA_CLOCK_REG);
    }
    else if (f <= 200000) {
	TGA_WRITE_REG(1, TGA_CLOCK_REG);
	TGA_WRITE_REG(0, TGA_CLOCK_REG);
    }
    else {
	TGA_WRITE_REG(0, TGA_CLOCK_REG);
	TGA_WRITE_REG(1, TGA_CLOCK_REG);
    }

    TGA_WRITE_REG(1, TGA_CLOCK_REG);
    TGA_WRITE_REG(0, TGA_CLOCK_REG);
    TGA_WRITE_REG(0, TGA_CLOCK_REG);
    TGA_WRITE_REG(1, TGA_CLOCK_REG);
    TGA_WRITE_REG(0, TGA_CLOCK_REG);
    TGA_WRITE_REG(1, TGA_CLOCK_REG);

    target = (f << shift) / TGA_PLL_BASE_FREQ;
    min_diff = TGA_PLL_MAX_FREQ;

    r = 7 / target;
    if (!r)
	r = 1;

    base = target * r;
    while (base < 449) {
	for (n = base < 7 ? 7 : base ; n < base + target && n < 449; n++) {
	m = ((n + 3) / 7) - 1;
	a = 0;
	DIFFCHECK((m + 1) * 7);
	m++;
	DIFFCHECK((m + 1) * 7);
	m = (n / 6) - 1;
	if( (a = n % 6))
	    DIFFCHECK( n );
	}
	r++;
	base += target;
    }

    vr--;

    for( r=0; r<8 ; r++) {
	TGA_WRITE_REG((vm >> r) & 1, TGA_CLOCK_REG);
    }
    for( r=0; r<8 ; r++) {
	TGA_WRITE_REG((va >> r) & 1, TGA_CLOCK_REG);
    }
    for( r=0; r<7 ; r++) {
	TGA_WRITE_REG((vr >> r) & 1, TGA_CLOCK_REG);
    }
    TGA_WRITE_REG(((vr >> 7) & 1)|2, TGA_CLOCK_REG);
}


static int tgafb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
                         u_int *transp, struct fb_info *info)
{
    if (regno > 255)
	return 1;
    *red = (palette[regno].red<<8) | palette[regno].red;
    *green = (palette[regno].green<<8) | palette[regno].green;
    *blue = (palette[regno].blue<<8) | palette[regno].blue;
    *transp = 0;
    return 0;
}


static int tgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
                         u_int transp, struct fb_info *info)
{
    if (regno > 255)
	return 1;
    red >>= 8;
    green >>= 8;
    blue >>= 8;
    palette[regno].red = red;
    palette[regno].green = green;
    palette[regno].blue = blue;

#ifdef FBCON_HAS_CFB32
    if (regno < 16 && fb_info.tga_type != TGA_TYPE_8PLANE)
	fbcon_cfb32_cmap[regno] = (red << 16) | (green << 8) | blue;
#endif

    if (fb_info.tga_type == TGA_TYPE_8PLANE) { 
        BT485_WRITE(regno, BT485_ADDR_PAL_WRITE);
        TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
        TGA_WRITE_REG(red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
        TGA_WRITE_REG(green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
        TGA_WRITE_REG(blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
    }                                                    
    /* How to set a single color register on 24-plane cards?? */

    return 0;
}

#if 1
    /*
     *	FIXME: since I don't know how to set a single arbitrary color register
     *  on 24-plane cards, all color palette registers have to be updated
     */

static int tgafb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
			  struct fb_info *info)
{
    int err;

    if (!fb_display[con].cmap.len) {	/* no colormap allocated? */
	if ((err = fb_alloc_cmap(&fb_display[con].cmap, 256, 0)))
	    return err;
    }
    if (con == currcon) {		/* current console? */
	err = fb_set_cmap(cmap, kspc, tgafb_setcolreg, info);
#if 1
	if (fb_info.tga_type != TGA_TYPE_8PLANE)
		tgafb_update_palette();
#endif
	return err;
    } else
	fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
    return 0;
}

static void tgafb_update_palette(void)
{
    int i;

    BT463_LOAD_ADDR(0x0000);
    TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG);

    for (i = 0; i < 256; i++) {
	 TGA_WRITE_REG(palette[i].red|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	 TGA_WRITE_REG(palette[i].green|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
	 TGA_WRITE_REG(palette[i].blue|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
    }
}
#endif


static int tgafb_blank(int blank, struct fb_info_gen *info)
{
    static int tga_vesa_blanked = 0;
    u32 vhcr, vvcr, vvvr;
    unsigned long flags;
    
    save_flags(flags);
    cli();

    vhcr = TGA_READ_REG(TGA_HORIZ_REG);
    vvcr = TGA_READ_REG(TGA_VERT_REG);
    vvvr = TGA_READ_REG(TGA_VALID_REG) & ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);

    switch (blank) {
    case 0: /* Unblanking */
        if (tga_vesa_blanked) {
	   TGA_WRITE_REG(vhcr & 0xbfffffff, TGA_HORIZ_REG);
	   TGA_WRITE_REG(vvcr & 0xbfffffff, TGA_VERT_REG);
	   tga_vesa_blanked = 0;
	}
 	TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
	break;

    case 1: /* Normal blanking */
	TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
	break;

    case 2: /* VESA blank (vsync off) */
	TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG);
	TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
	tga_vesa_blanked = 1;
	break;

    case 3: /* VESA blank (hsync off) */
	TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG);
	TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
	tga_vesa_blanked = 1;
	break;

    case 4: /* Poweroff */
	TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG);
	TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG);
	TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
	tga_vesa_blanked = 1;
	break;
    }

    restore_flags(flags);
    return 0;
}


static void tgafb_set_disp(const void *fb_par, struct display *disp,
	struct fb_info_gen *info)
{
    disp->screen_base = (char *)fb_info.tga_fb_base;
    switch (fb_info.tga_type) {
#ifdef FBCON_HAS_CFB8
	case TGA_TYPE_8PLANE:
	    disp->dispsw = &fbcon_cfb8;
            break;
#endif
#ifdef FBCON_HAS_CFB32
        case TGA_TYPE_24PLANE:
        case TGA_TYPE_24PLUSZ:
	    disp->dispsw = &fbcon_cfb32; 
            disp->dispsw_data = &fbcon_cfb32_cmap;
            break;
#endif
        default:
            disp->dispsw = &fbcon_dummy;
    }

    disp->scrollmode = SCROLL_YREDRAW;
}


struct fbgen_hwswitch tgafb_hwswitch = {
    tgafb_detect, tgafb_encode_fix, tgafb_decode_var, tgafb_encode_var, tgafb_get_par,
    tgafb_set_par, tgafb_getcolreg, tgafb_setcolreg, NULL, tgafb_blank, 
    tgafb_set_disp
};


    /*
     *  Hardware Independent functions
     */


    /* 
     *  Frame buffer operations
     */

static struct fb_ops tgafb_ops = {
	owner:		THIS_MODULE,
	fb_get_fix:	fbgen_get_fix,
	fb_get_var:	fbgen_get_var,
	fb_set_var:	fbgen_set_var,
	fb_get_cmap:	fbgen_get_cmap,
	fb_set_cmap:	tgafb_set_cmap,
};


#ifndef MODULE
    /*
     *  Setup
     */

int __init tgafb_setup(char *options) {
    char *this_opt;
    int i;
    
    if (options && *options) {
    	while ((this_opt = strsep(&options, ",")) != NULL) {
       	    if (!*this_opt) { continue; }
        
	    if (!strncmp(this_opt, "font:", 5)) {
	     	strncpy(default_fontname, this_opt+5, sizeof default_fontname);
	    }

	    else if (!strncmp(this_opt, "mode:", 5)) {
    		for (i = 0; i < NUM_TOTAL_MODES; i++) {
    		    if (!strcmp(this_opt+5, tgafb_predefined[i].name))
    			default_var = tgafb_predefined[i].var;
		    	default_var_valid = 1;
    		}
    	    } 
	    
	    else {
      		printk(KERN_ERR "tgafb: unknown parameter %s\n", this_opt);
    	    }
      	}
    }
    return 0;
}
#endif


    /*
     *  Initialisation
     */

int __init tgafb_init(void)
{
    struct pci_dev *pdev;

    pdev = pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, NULL);
    if (!pdev)
	return -ENXIO;

    /* divine board type */

    fb_info.tga_mem_base = (unsigned long)ioremap(pdev->resource[0].start, 0);
    fb_info.tga_type = (readl(fb_info.tga_mem_base) >> 12) & 0x0f;
    fb_info.tga_regs_base = fb_info.tga_mem_base + TGA_REGS_OFFSET;
    fb_info.tga_fb_base = (fb_info.tga_mem_base
			   + fb_offset_presets[fb_info.tga_type]);
    pci_read_config_byte(pdev, PCI_REVISION_ID, &fb_info.tga_chip_rev);

    /* setup framebuffer */

    fb_info.gen.info.node = -1;
    fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT;
    fb_info.gen.info.fbops = &tgafb_ops;
    fb_info.gen.info.disp = &disp;
    fb_info.gen.info.changevar = NULL;
    fb_info.gen.info.switch_con = &fbgen_switch;
    fb_info.gen.info.updatevar = &fbgen_update_var;
    fb_info.gen.info.blank = &fbgen_blank;
    strcpy(fb_info.gen.info.fontname, default_fontname);
    fb_info.gen.parsize = sizeof (struct tgafb_par);
    fb_info.gen.fbhw = &tgafb_hwswitch;
    fb_info.gen.fbhw->detect();

    printk (KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n", fb_info.tga_chip_rev);
    printk (KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n", 
	    pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
	    
    switch (fb_info.tga_type) 
    { 
	case TGA_TYPE_8PLANE:
	    strcpy (fb_info.gen.info.modename,"Digital ZLXp-E1"); 
	    break;

	case TGA_TYPE_24PLANE:
	    strcpy (fb_info.gen.info.modename,"Digital ZLXp-E2"); 
	    break;

	case TGA_TYPE_24PLUSZ:
	    strcpy (fb_info.gen.info.modename,"Digital ZLXp-E3"); 
	    break;
    }

    /* This should give a reasonable default video mode */

    if (!default_var_valid) {
	default_var = tgafb_predefined[0].var;
    }
    fbgen_get_var(&disp.var, -1, &fb_info.gen.info);
    disp.var.activate = FB_ACTIVATE_NOW;
    fbgen_do_set_var(&disp.var, 1, &fb_info.gen);
    fbgen_set_disp(-1, &fb_info.gen);
    fbgen_install_cmap(0, &fb_info.gen);
    if (register_framebuffer(&fb_info.gen.info) < 0)
	return -EINVAL;
    printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n", 
	    GET_FB_IDX(fb_info.gen.info.node), fb_info.gen.info.modename, 
	    pdev->resource[0].start);
    return 0;
}


    /*
     *  Cleanup
     */

void __exit tgafb_cleanup(void)
{
    unregister_framebuffer(&fb_info.gen.info);
}


    /*
     *  Modularisation
     */

#ifdef MODULE
MODULE_LICENSE("GPL");
module_init(tgafb_init);
#endif

module_exit(tgafb_cleanup);