mq200fb.h

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

/* window 1 start address */
union gc0cr {
    struct {
       u32 w1sa        :21;    /* window 1 start address */
       u32 reserved_1  :11;
    }  part;
    u32 whole;
};

/* window 1 stride */
union gc0er {
    struct {
       s16 w1st;               /* window 1 stride */
       s16 aw1st;              /* alternate window 1 stride */
    }  part;
    u32 whole;
};

/* hardware cursor 1 position */
union gc10r {
    struct {
       u32 hc1s        :12;    /* horizontal cursor 1 start */
       u32 reserved_1  :4;
       u32 vc1s        :12;    /* vertical cursor 1 start */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* hardware cursor 1 start address and offset */
union gc11r {
    struct {
       u32 hc1sa       :11;    /* hardware cursor 1 start address */
       u32 reserved_1  :5;
       u32 hc1o        :6;     /* horizontal cursor 1 offset */
       u32 reserved_2  :2;
       u32 vc1o        :6;     /* vertical cursor 1 offset */
       u32 reserved_3  :2;
    }  part;
    u32 whole;
};

/* hardware cursor 1 foreground color */
union gc12r {
    struct {
       u32 hc1fc       :24;    /* hardware cursor 1 foreground color */
       u32 reserved_1  :8;
    }  part;
    u32 whole;
};

/* hardware cursor 1 background color */
union gc13r {
    struct {
       u32 hc1bc       :24;    /* hardware cursor 1 background color */
       u32 reserved_1  :8;
    }  part;
    u32 whole;
};

/* graphics controller color pallete */
union c1xxr {
    struct {
       u8 red;                 /* red color pallete */
       u8 green;               /* green/gray color pallete */
       u8 blue;                /* blue color palette */
       u8 reserved_1;
    }  part;
    u32 whole;
};

/* devicee configuration register 0 */
union dc00r {
    struct {
       u32 osc_bypass  :1;     /* oscillator bypass */
       u32 osc_enbl    :1;     /* oscillator enable */
       u32 pll1_bypass :1;     /* PLL1 bypass */
       u32 pll1_enbl   :1;     /* PLL1 enable */
       u32 pll1_p_par  :3;     /* PLL1 P parameter */
       u32 cpu_div     :1;     /* CPU interface clock divisor */
       u32 pll1_n_par  :5;     /* PLL1 N parameter */
       u32 saisc       :1;     /* StrongARM interface synchronizer control */
       u32 s_chp_reset :1;     /* software chip reset */
       u32 mem_enbl    :1;     /* memory standby enable */
       u32 pll1_m_par  :8;     /* PLL 1 M parameter */
       u32 osc_shaper  :1;     /* oscillator shaper disable */
       u32 fast_pwr    :1;     /* fast power sequencing */
       u32 osc_frq     :2;     /* oscillator frequency select */
       u32 pll1_trim   :4;     /* PLL 1 trim value */
    }  part;
    u32 whole;
};

/* primary drawing command register */
union ge00r {
    struct {
       u32 rop         :8;     /* raster operation */
       /**/
       u32 cmd_typ     :3;     /* command type */
       u32 x_dir       :1;     /* x direction */
       u32 y_dir       :1;     /* y direction */
       u32 src_mem     :1;     /* source memory */
       u32 mon_src     :1;     /* mono source */
       u32 mon_ptn     :1;     /* mono pattern */
       /**/
       u32 dst_trns_e  :1;     /* destination transparency enable */
       u32 dst_trns_p  :1;     /* destination transparency polarity */
       u32 mon_trns_e  :1;     /* mono source or mono pattern transparency
                                  enable */
       u32 mon_trns_p  :1;     /* mono transparency polarity */
       u32 mod_sel     :1;     /* memory to screen or off screen to screen
                                  mode select */
       u32 alpha_sel   :2;     /* Alpha byte mask selection */
       u32 sol_col     :1;     /* solid color */
       /**/
       u32 stride_eq   :1;     /* source stride is equal to destination
                                  stride */
       u32 rop2_sel    :1;     /* ROP2 code selection */
       u32 clipping    :1;     /* enable clipping */
       u32 auto_exec   :1;     /* auto execute */
       u32 reserved_1  :4;
    }  part;
    u32 whole;
};

/* primary width and height register */
union ge01r {
    struct {
       u32 width       :12;    /* source/destination window width */
       u32 reserved_1  :4;

       u32 height      :12;    /* source/destination window height */
       u32 reserved_2  :1;
       u32 reserved_3  :3;
    }  bitblt;
    struct {
       u32 dm          :17;
       u32 axis_major  :12;
       u32 x_y         :1;     /* x-major or y-major */
       u32 last_pix    :1;     /* decision to draw or not to draw the last
                                  pixel of the line */
       u32 reserved_1  :1;
    }  bresenham;
    u32 whole;
};

/* primary destination address register */
union ge02r {
    struct {
       u32 dst_x       :12;    /* destination x position */
       u32 reserved_1  :1;
       u32 h_offset    :3;     /* mono/color pattern horizontal offset */

       u32 dst_y       :12;    /* destination y position */
       u32 reserved_2  :1;
       u32 v_offset    :3;     /* mono/color pattern vertical offset */
    }  window;
    struct {
       u32 x           :12;    /* starting x coordinate */
       u32 dm          :17;    /* 17 bits major-axis delta */
       u32 reserved_1  :3;
    }  line;
    u32 whole;
};

/* source XY register/line draw starting Y coordinate and mintor axis delta */
union ge03r {
    struct {
       u32 src_x       :12;    /* source X position */
       u32 reserved_1  :4;

       u32 src_y       :12;    /* source Y position */
       u32 reserved_2  :4;
    }  window;
    struct {
       u32 start_y     :12;    /* starting Y coordinate */
       u32 dn          :17;    /* 17 bits minor-axis delta */
       u32 reserved_1  :3;
    }  line;
    u32 whole;
};

/* clip left/top register */
union ge05r {
    struct {
       u32 left        :12;    /* left edge of clipping rectangle */
       u32 reserved_1  :4;

       u32 top         :12;    /* top edge of clipping rectangle */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* source stride/offset register */
union ge09r {
    struct {
       u32 src_strid   :12;    /* source line stride */
       u32 reserved_1  :13;
       u32 strt_bit    :3;     /* initial mono source bit offset */
       u32 strt_byte   :3;     /* initial mono/color source byte offset */
       u32 reserved_2  :1;
    }  line;
    struct {
       u32 strt_bit    :5;     /* initial mono source bit offset */
       u32 reserved_1  :1;
       u32 amount      :10;    /* number of 16 bytes amount that MIU need
                                  to fetch from frame buffer */

       u32 reserved_2  :9;
       u32 bit_spc     :7;     /* bit space between lines */
    }  pack_mono;
    struct {
       u32 strt_bit    :3;     /* initial mono source bit offset */
       u32 strt_byte   :3;     /* initial mono/color source byte offset */
       u32 amount      :10;    /* number of 16 bytes amount that MIU need
                                  to fetch from frame buffer */

       u32 reserved_1  :9;
       u32 bit_spc     :3;     /* bit space between lines */
       u32 byt_spc     :4;     /* byte space between lines */
    }  pack_color;
    u32 whole;
};

/* destination stride register and color depth */
union ge0ar {
    struct {
       u32 dst_strid   :12;    /* destination line stride and color depth */
       u32 reserved_1  :18;
       u32 col_dpth    :2;     /* color depth */
    }  part;
    u32 whole;
};

/* device ID/vendor ID register */
union pc00r {
    struct {
       u16 device;             /* device ID */
       u16 vendor;             /* vendor ID */
    }  part;
    u32 whole;
};

/* command/status register */
union pc04r {
    struct {
       /* command register */
       u32 io_spc      :1;     /* IO space control */
       u32 mem_spc     :1;     /* memory space control */
       u32 bus_master  :1;     /* bus master control */
       u32 special_cyc :1;     /* special cycle */
       u32 mem_w_invld :1;     /* memory write and invalidate */
       u32 vga_palette :1;     /* VGA palette snoop */
       u32 parity_chk  :1;     /* parity error checking enable */
       u32 adr_dat_stp :1;     /* address/data stepping */
       u32 serr_enbl   :1;     /* SERR# enable */
       u32 reserved_1  :7;
       /* status register */
       u32 reserved_2  :5;
       u32 mhz_66      :1;     /* 66 MHz capability */
       u32 usr_def     :1;     /* user definable features supported */
       u32 fast_b_b    :1;     /* fast back-to-back capability */
       u32 reserved_3  :1;
       u32 devsel_tim  :2;     /* DEVSEL timing */
       u32 sig_tgt_abt :1;     /* signaled target abort */
       u32 reserved_4  :2;
       u32 serr_assert :1;     /* SERR# assertion */
       u32 parity_dtct :1;     /* parity error detect */
    }  part;
    u32 whole;
};


/****
 * Others
 */

#define CHIPNAME "MQ-200"
#define DEVICE_DRIVER_NAME "mq200fb"
#define CURSOR_BLINK_RATE (HZ * 20 / 100)


#endif