mq200fb.h

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

       u32 cur1_enbl   :1;     /* D2 cursor 1 enable */
       u32 reserved_3  :4;

       u32 ctl2_enbl   :1;     /* D2 controller 2 enable */
       u32 win2_enbl   :1;     /* D2 window 2 enable */
       u32 awin2_enbl  :1;     /* D2 alternate window 2 enable */
       u32 cur2_enbl   :1;     /* D2 cursor 2 enable */
       u32 reserved_4  :4;
    }  part;
    u32 whole;
};

/* PLL 2 programming */
union pm06r {
    struct {
       u32 clk_src     :1;     /* PLL 2 reference clock source */
       u32 bypass      :1;     /* PLL 2 bypass */
       u32 reserved_1  :2;
       u32 p_par       :3;     /* PLL 2 P parameter */
       u32 reserved_2  :1;

       u32 n_par       :5;     /* PLL 2 N parameter */
       u32 reserved_3  :3;

       u32 m_par       :8;     /* PLL 2 M parameter */

       u32 reserved_4  :4;
       u32 trim        :4;     /* PLL 2 trim value */
    }  part;
    u32 whole;
};

/* PLL 3 programming */
union pm07r {
    struct {
       u32 clk_src     :1;     /* PLL 3 reference clock source */
       u32 bypass      :1;     /* PLL 3 bypass */
       u32 reserved_1  :2;
       u32 p_par       :3;     /* PLL 3 P parameter */
       u32 reserved_2  :1;

       u32 n_par       :5;     /* PLL 3 N parameter */
       u32 reserved_3  :3;

       u32 m_par       :8;     /* PLL 3 M parameter */

       u32 reserved_4  :4;
       u32 trim        :4;     /* PLL 3 trim value */
    }  part;
    u32 whole;
};

/* source FIFO/command FIFO/GE status register */
union cc01r {
    struct {
       u32 cmd_fifo    :5;     /* command FIFO status register */
       u32 reserved_1  :3;

       u32 src_fifo    :4;     /* source FIFO status register */
       u32 reserved_2  :4;

       u32 ge_busy     :1;     /* GE is busy */
       u32 reserved_3  :7;

       u32 reserved_4  :8;
    }  part;
    u32 whole;
};

/* MIU interface control 1 */
union mm00r {
    struct {
       u32 miu_enbl    :1;     /* MIU enable bit */
       u32 mr_dsbl     :1;     /* MIU reset disable bit */
       u32 edr_dsbl    :1;     /* embedded DRAM reset disable bit */
       u32 reserved_1  :29;
    }  part;
    u32 whole;
};

/* MIU interface control 2 */
union mm01r {
    struct {
       u32 mc_src      :1;     /* memory clock source */
       u32 msr_enbl    :1;     /* memory slow refresh enable bit */
       u32 pb_cpu      :1;     /* page break enable for CPU */
       u32 pb_gc1      :1;     /* page break enable for GC1 */
       u32 pb_gc2      :1;     /* page break enable for GC2 */
       u32 pb_stn_r    :1;     /* page break enable for STN read */
       u32 pb_stn_w    :1;     /* page break enable for STN write */
       u32 pb_ge       :1;     /* page break enable for GE */
       u32 reserved_1  :4;
       u32 mr_interval :14;    /* normal memory refresh time interval */
       u32 reserved_2  :4;
       u32 edarm_enbl  :1;     /* embedded DRAM auto-refresh mode enable */
       u32 eds_enbl    :1;     /* EDRAM standby enable for EDRAM normal
                                  mode operation */
    }  part;
    u32 whole;
};

/* memory interface control 3 */
union mm02r {
    struct {
       u32 bs_         :2;
       u32 bs_stnr     :2;     /* burst count for STN read memory cycles */
       u32 bs_stnw     :2;     /* burst count for STN write memroy cycles */
       u32 bs_ge       :2;     /* burst count for graphics engine
                                  read/write memroy cycles */
       u32 bs_cpuw     :2;     /* burst count for CPU write memory cycles */
       u32 fifo_gc1    :4;     /* GC1 display refresh FIFO threshold */
       u32 fifo_gc2    :4;     /* GC2 display refresh FIFO threshold */
       u32 fifo_stnr   :4;     /* STN read FIFO threshold */
       u32 fifo_stnw   :4;     /* STN write FIFO threshold */
       u32 fifo_ge_src :3;     /* GE source read FIFO threshold */
       u32 fifo_ge_dst :3;     /* GE destination read FIFO threshold */
    }  part;
    u32 whole;
};

/* memory interface control 4 */
union mm03r {
    struct {
       u32 rd_late_req :1;     /* read latency request */
       u32 reserved_1  :31;
    }  part;
    u32 whole;
};

/* memory interface control 5 */
union mm04r {
    struct {
       u32 latency     :3;     /* EDRAM latency */
       u32 dmm_cyc     :1;     /* enable for the dummy cycle insertion
                                  between read and write cycles */
       u32 pre_dmm_cyc :1;     /* enable for the dummy cycle insertion
                                  between read/write and precharge cycles
                                  for the same bank */
       u32 reserved_1  :3;
       u32 bnk_act_cls :2;     /* bank activate command to bank close
                                  command timing interval control */
       u32 bnk_act_rw  :1;     /* bank activate command to read/wirte
                                  command timing interval control */
       u32 bnk_cls_act :1;     /* bank close command to bank activate
                                  command timing interval control */
       u32 trc         :1;     /* row cycle time */
       u32 reserved_2  :3;
       u32 delay_r     :2;     /* programmable delay for read clock */
       u32 delay_m     :2;     /* programmable delay for internal memory
                                  clock */
    }  part;
    u32 whole;
};

/* graphics controller 1 register */
union gc00r {
    struct {
       u32 ctl_enbl    :1;     /* Controller 1 Enable */
       u32 hc_reset    :1;     /* Horizontal Counter 1 Reset */
       u32 vc_reset    :1;     /* Vertical Counter 1 Reset */
       u32 iwin_enbl   :1;     /* Image Window 1 Enable */
       u32 gcd         :4;     /* Graphics Color Depth (GCD) */

       u32 hc_enbl     :1;     /* Hardware Cursor 1 Enable */
       u32 reserved_1  :2;
       u32 aiwin_enbl  :1;     /* Alternate Image Window Enable */
       u32 agcd        :4;     /* Alternate Graphics Color Depth (AGCD) */

       u32 g1rclk_src  :2;     /* G1RCLK Source */
       u32 tm0         :1;     /* Test Mode 0 */
       u32 tm1         :1;     /* Test Mode 1 */
       u32 fd          :3;     /* G1MCLK First Clock Divisor (FD1) */
       u32 reserved_2  :1;

       u32 sd          :8;     /* G1MCLK Second Clock Divisor (SD1) */
    }  part;
    u32 whole;
};

/* graphics controller CRT control */
union gc01r {
    struct {
       u32 dac_enbl    :2;     /* CRT DAC enable */
       u32 hsync_out   :1;     /* CRT HSYNC output during power down mode */
       u32 vsync_out   :1;     /* CRT VSYNC output during power down mode */
       u32 hsync_ctl   :2;     /* CRT HSYNC control */
       u32 vsync_ctl   :2;     /* CRT VSYNC control */
       /**/
       u32 hsync_pol   :1;     /* CRT HSYNC polarity */
       u32 vsync_pol   :1;     /* CRT VSYNC polarity */
       u32 sync_p_enbl :1;     /* sync pedestal enable */
       u32 blnk_p_enbl :1;     /* blank pedestal enable */
       u32 c_sync_enbl :1;     /* composite sync enable */
       u32 vref_sel    :1;     /* VREF select */
       u32 mn_sns_enbl :1;     /* monitor sense enable */
       u32 ct_out_enbl :1;     /* constant output enable */
       /**/
       u32 dac_out_lvl :8;     /* monitor sense DAC output level */
       /**/
       u32 blue_dac_r  :1;     /* blue DAC sense result */
       u32 green_dac_r :1;     /* green DAC sense result */
       u32 red_dac_r   :1;     /* red DAC sense result */
       u32 reserved_1  :1;
       u32 mon_col_sel :1;     /* mono/color monitor select */
       u32 reserved_2  :3;
    }  part;
    u32 whole;
};

/* horizontal display 1 control */
union gc02r {
    struct {
       u32 hd1t        :12;    /* horizontal display 1 total */
       u32 reserved_1  :4;

       u32 hd1e        :12;    /* horizontal display 1 end */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* vertical display 1 control */
union gc03r {
    struct {
       u32 vd1t        :12;    /* vertical display 1 total */
       u32 reserved_1  :4;

       u32 vd1e        :12;    /* vertical display 1 end */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* horizontal sync 1 control */
union gc04r {
    struct {
       u32 hs1s        :12;    /* horizontal sync 1 start */
       u32 reserved_1  :4;

       u32 hs1e        :12;    /* horizontal sync 1 end */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* vertical sync 1 control */
union gc05r {
    struct {
       u32 vs1s        :12;    /* vertical sync 1 start */
       u32 reserved_1  :4;

       u32 vs1e        :12;    /* vertical sync 1 end */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};

/* vertical display 1 count */
union gc07r {
    struct {
       u32 vd_cnt      :12;    /* vertical display 1 count */
       u32 reverved_1  :20;
    }  part;
    u32 whole;
};

/* horizontal window 1 control */
union gc08r {
    struct {
       u32 hw1s        :12;    /* horizontal window 1 start (HW1S) */
       u32 reserved_1  :4;

       u32 hw1w        :12;    /* horizontal window 1 width (HW1W) */
       u32 w1ald       :4;     /* window 1 additional line data */
    }  part;
    u32 whole;
};

/* vertical window 1 control */
union gc09r {
    struct {
       u32 vw1s        :12;    /* vertical window 1 start */
       u32 reserved_1  :4;
       u32 vw1h        :12;    /* vertical window 1 height */
       u32 reserved_2  :4;
    }  part;
    u32 whole;
};