mq200fb.h

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

#ifndef __MQ200_FB_H__
#define __MQ200_FB_H__

#ifdef CONFIG_SH_KEYWEST
#include <asm/hitachi_keywest.h>
#endif


/****
 * Addresses of Module
 */
#define MQ200_FB_BASE  (MQ200_IOBASE + 0x1800000) /* framebuffer */
#define MQ200_FB_SIZE 0x200000 /* framebuffer size in bytes */
#define MQ200_REGS_BASE (MQ200_IOBASE + 0x1e00000) /* start of registers area */
#define MQ200_REGS_SIZE 0x200000 /* registers area size */
#define PMU_OFFSET 0x00000     /* power management */
#define CPU_OFFSET 0x02000     /* CPU interface */
#define MIU_OFFSET 0x04000     /* memory controller */
#define IN_OFFSET  0x08000     /* interrupt controller */
#define GC_OFFSET  0x0a000     /* graphics controller 1&2 */
#define GE_OFFSET  0x0c000     /* graphics engine */
#define FPI_OFFSET 0x0e000     /* flat panel controller */
#define CP1_OFFSET 0x10000     /* color palette 1 */
#define DC_OFFSET  0x14000     /* device configuration */
#define PCI_OFFSET 0x16000     /* PCI configuration */
#define PSF_OFFSET 0x18000     /* ??? */
#define CURSOR_IMAGE_SIZE 2048 /* cursor image size */
#define CURSOR_OFFSET (MQ200_FB_SIZE - CURSOR_IMAGE_SIZE) /* cursor image
                                                            offset */


/****
 * Registers
 */

/* power management unit */
#define PMR(fb_info) ((fb_info)->pci_base + 0x40)/* power management
                                                   register */
#define PMR_VALUE 0x06210001   /* expected read value of PMR register */
#define PMCSR(fb_info) ((fb_info)->pci_base + 0x44) /* power management
                                                      control/status
                                                      register */
#define PM00R(fb_info) ((fb_info)->pmu_base + 0x00) /* power management unit
                                                      configuration
                                                      register */
#define PM01R(fb_info) ((fb_info)->pmu_base + 0x04) /* D1 state control */
#define PM02R(fb_info) ((fb_info)->pmu_base + 0x08) /* d2 state control */
#define PM06R(fb_info) ((fb_info)->pmu_base + 0x18) /* PLL 2 programming */
#define PM07R(fb_info) ((fb_info)->pmu_base + 0x1c) /* PLL 3 programming */

/* CPU interface */
#define CC01R(fb_info) ((fb_info)->cpu_base + 0x04)/* source FIFO/command
                                                     FIFO/GE status
                                                     register */

/* memory interface unit */
#define MM00R(fb_info) ((fb_info)->miu_base + 0x00)/* MIU interface control
                                                     1 */
#define MM01R(fb_info) ((fb_info)->miu_base + 0x04) /* MIU interface control
                                                      2 */
#define MM02R(fb_info) ((fb_info)->miu_base + 0x08) /* memory itnerface
                                                      control 3 */
#define MM03R(fb_info) ((fb_info)->miu_base + 0x0c) /* memory interface
                                                      control 4 */
#define MM04R(fb_info) ((fb_info)->miu_base + 0x10) /* memory interface
                                                      control 5 */

/* interrupt controller */
#define IN00R(fb_info) ((fb_info)->in_base + 0x00)/* global interrupt
                                                    control register */
#define IN01R(fb_info) ((fb_info)->in_base + 0x04) /* interrupt mask
                                                     register */
#define IN02R(fb_info) ((fb_info)->in_base + 0x08) /* interrupt status
                                                     register */
#define IN03R(fb_info) ((fb_info)->in_base + 0x0c) /* interrupt pin raw
                                                     status */

/* graphics controller 1 module */
#define GC00R(fb_info) ((fb_info)->gc_base + 00)/* graphics controller 1
                                                  control */
enum {
    /* color palette enabled */
    GCD_1_CP, GCD_2_CP, GCD_4_CP, GCD_8_CP,
    GCD_16_CP, GCD_24_CP, GCD_32_RGB_CP, GCD_32_BGR_CP,
    /* coloer palette bypassed */
    GCD_16 = 12, GCD_24, GCD_32_RGB, GCD_32_BGR
};

#define GC01R(fb_info) ((fb_info)->gc_base + 0x04) /* graphics controller
                                                     CRT control */
#define GC02R(fb_info) ((fb_info)->gc_base + 0x08) /* horizontal display 1
                                                     control */
#define GC03R(fb_info) ((fb_info)->gc_base + 0x0c) /* vertical display 1
                                                     control */
#define GC04R(fb_info) ((fb_info)->gc_base + 0x10) /* horizontal sync 1
                                                     control */
#define GC05R(fb_info) ((fb_info)->gc_base + 0x14) /* vertical sync 1
                                                     control */
#define GC07R(fb_info) ((fb_info)->gc_base + 0x1c) /* vertical display 1
                                                     count */
#define GC08R(fb_info) ((fb_info)->gc_base + 0x20) /* horizontal window 1
                                                     control */
#define GC09R(fb_info) ((fb_info)->gc_base + 0x24) /* vertical window 1
                                                     control */
#define GC0AR(fb_info) ((fb_info)->gc_base + 0x28) /* alternate horizontal
                                                     window 1 control */
#define GC0BR(fb_info) ((fb_info)->gc_base + 0x2c) /* alternate vertical
                                                     window 1 control */
#define GC0CR(fb_info) ((fb_info)->gc_base + 0x30) /* window 1 start address
                                                   */
#define GC0DR(fb_info) ((fb_info)->gc_base + 0x34) /* alternate window 1
                                                     start address */
#define GC0ER(fb_info) ((fb_info)->gc_base + 0x38) /* window 1 stride */
#define GC0FR(fb_info) ((fb_info)->gc_base + 0x3c) /* reserved */
#define GC10R(fb_info) ((fb_info)->gc_base + 0x40) /* hardware cursor 1
                                                     position */
#define GC11R(fb_info) ((fb_info)->gc_base + 0x44) /* hardware cursor 1
                                                     start address and
                                                     offset */
#define GC12R(fb_info) ((fb_info)->gc_base + 0x48) /* hardware cursor 1
                                                     foreground color */
#define GC13R(fb_info) ((fb_info)->gc_base + 0x4c) /* hardware cursor 1
                                                     background color */

/* graphics engine */
#define GE00R(fb_info) ((fb_info)->ge_base + 0x00)/* primary drawing command
                                                    register */
#define ROP_SRCCOPY    0xCC    /* dest = source */
#define ROP_SRCPAINT   0xEE    /* dest = source OR dest */
#define ROP_SRCAND     0x88    /* dest = source AND dest */
#define ROP_SRCINVERT  0x66    /* dest = source XOR dest */
#define ROP_SRCERASE   0x44    /* dest = source AND (NOT dest) */
#define ROP_NOTSRCCOPY 0x33    /* dest = NOT source */
#define ROP_NOTSRCERASE        0x11    /* dest = (NOT source) AND (NOT dest) */
#define ROP_MERGECOPY  0xC0    /* dest = source AND pattern */
#define ROP_MERGEPAINT 0xBB    /* dest = (NOT source) OR dest */
#define ROP_PATCOPY    0xF0    /* dest = pattern */
#define ROP_PATPAINT   0xFB    /* dest = DPSnoo */
#define ROP_PATINVERT  0x5A    /* dest = pattern XOR dest */
#define ROP_DSTINVERT  0x55    /* dest = NOT dest */
#define ROP_BLACKNESS  0x00    /* dest = BLACK */
#define ROP_WHITENESS  0xFF    /* dest = WHITE */
#define GE01R(fb_info) ((fb_info)->ge_base + 0x04) /* primary width and
                                                     height register */
#define GE02R(fb_info) ((fb_info)->ge_base + 0x08) /* primary destination
                                                     address register */
#define GE03R(fb_info) ((fb_info)->ge_base + 0x0c) /* primary source XY
                                                     register */
#define GE04R(fb_info) ((fb_info)->ge_base + 0x10) /* primary color compare
                                                     register */
#define GE05R(fb_info) ((fb_info)->ge_base + 0x14) /* primary clip left/top
                                                     register */
#define GE06R(fb_info) ((fb_info)->ge_base + 0x18) /* primary clip
                                                     right/bottom register
                                                  */
#define GE07R(fb_info) ((fb_info)->ge_base + 0x1c) /* primary source and
                                                     pattern offset
                                                     register */
#define GE08R(fb_info) ((fb_info)->ge_base + 0x20) /* primary foreground
                                                     color
                                                     register/rectangle
                                                     fill register */
#define GE09R(fb_info) ((fb_info)->ge_base + 0x24) /* source stride/offset
                                                     register */
#define GE0AR(fb_info) ((fb_info)->ge_base + 0x28) /* destination stride
                                                     register and color
                                                     depth */
#define GE0BR(fb_info) ((fb_info)->ge_base + 0x2c) /* image base address
                                                     register */
#define GE40R(fb_info) ((fb_info)->ge_base + 0x100) /* mono pattern register
                                                      0 */
#define GE41R(fb_info) ((fb_info)->ge_base + 0x104) /* mono pattern register
                                                      1 */
#define GE42R(fb_info) ((fb_info)->ge_base + 0x108) /* foreground color
                                                      register */
#define GE43R(fb_info) ((fb_info)->ge_base + 0x10c) /* background color
                                                      register */

/* color palette */
#define C1xxR(fb_info, regno) \
       ((fb_info)->cp1_base + (regno) * 4) /* graphics controller color
                                              palette 1 */

/* device configuration */
#define DC00R(fb_info) ((fb_info)->dc_base + 0x00)/* device configuration
                                                    register 0 */

/* PCI configuration space */
#define PC00R(fb_info) ((fb_info)->pci_base + 0x00)/* device ID/vendor ID
                                                     register */
#define PC00R_VALUE 0x02004d51
#define PC04R(fb_info) ((fb_info)->pci_base + 0x04) /* command/status
                                                      register */

/* ??? */
#define PSF(fb_info) ((fb_info)->psf_base + 0x00)


/****
 * structure declarations
 */


/* power management miscellaneous control */
union pm00r {
    struct {
       u32 pll1_n_b5   :1;     /* PLL 1 N parameter bit 5 is 0 */
       u32 reserved_1  :1;
       u32 pll2_enbl   :1;     /* PLL 2 enable */
       u32 pll3_enbl   :1;     /* PLL 3 enable */
       u32 reserved_2  :1;
       u32 pwr_st_ctrl :1;     /* power state status control */
       u32 reserved_3  :2;

       u32 ge_enbl     :1;     /* graphics engine enable */
       u32 ge_bsy_gl   :1;     /* graphics engine force busy (global) */
       u32 ge_bsy_lcl  :1;     /* graphics engine force busy (local) */
       u32 ge_clock    :2;     /* graphics engine clock select */
       u32 ge_cmd_fifo :1;     /* graphics engine command FIFO reset */
       u32 ge_src_fifo :1;     /* graphics engine CPU source FIFO reset */
       u32 miu_pwr_seq :1;     /* memory interface unit power sequencing
                                  enable */

       u32 d3_mem_rfsh :1;     /* D3 memory refresh */
       u32 d4_mem_rfsh :1;     /* D4 memory refresh */
       u32 gpwr_intrvl :2;     /* general power sequencing interval */
       u32 fppwr_intrvl:2;     /* flat panel power sequencing interval */
       u32 gpwr_seq_ctr:1;     /* general power sequencing interval control */
       u32 pmu_tm      :1;     /* PMU test mode */

       u32 pwr_state   :2;     /* power state (read only) */
       u32 pwr_seq_st  :1;     /* power sequencing active status (read
                                  only) */
       u32 reserved_4  :5;
    }  part;
    u32 whole;
};

/* D1 state control */
union pm01r {
    struct {
       u32 osc_enbl    :1;     /* D1 oscillator enable */
       u32 pll1_enbl   :1;     /* D1 PLL 1 enable */
       u32 pll2_enbl   :1;     /* D1 PLL 2 enable */
       u32 pll3_enbl   :1;     /* D1 PLL 3 enable */
       u32 miu_enbl    :1;     /* D1 Memory Interface Unit (MIU) enable */
       u32 mem_rfsh    :1;     /* D1 memory refresh enable */
       u32 ge_enbl     :1;     /* D1 Graphics Engine (GE) enable */
       u32 reserved_1  :1;

       u32 crt_enbl    :1;     /* D1 CRT enable */
       u32 fpd_enbl    :1;     /* D1 Flat Panel enable */
       u32 reserved_2  :6;

       u32 ctl1_enbl   :1;     /* D1 controller 1 enable */
       u32 win1_enbl   :1;     /* D1 window 1 enable */
       u32 awin1_enbl  :1;     /* D1 alternate window 1 enable */
       u32 cur1_enbl   :1;     /* D1 cursor 1 enable */
      u32 reserved_3  :4;

       u32 ctl2_enbl   :1;     /* D1 controller 2 enable */
       u32 win2_enbl   :1;     /* D1 window 2 enable */
       u32 awin2_enbl  :1;     /* D1 alternate window 2 enable */
       u32 cur2_enbl   :1;     /* D1 cursor 2 enable */
       u32 reserved_4  :4;
    }  part;
    u32 whole;
};

/* D2 state control */
union pm02r {
    struct {
       u32 osc_enbl    :1;     /* D2 oscillator enable */
       u32 pll1_enbl   :1;     /* D2 PLL 1 enable */
       u32 pll2_enbl   :1;     /* D2 PLL 2 enable */
       u32 pll3_enbl   :1;     /* D2 PLL 3 enable */
       u32 miu_enbl    :1;     /* D2 Memory Interface Unit (MIU) enable */
       u32 mem_rfsh    :1;     /* D2 memory refresh enable */
       u32 ge_enbl     :1;     /* D2 Graphics Engine (GE) enable */
       u32 reserved_1  :1;

       u32 crt_enbl    :1;     /* D2 CRT enable */
       u32 fpd_enbl    :1;     /* D2 Flat Panel enable */
       u32 reserved_2  :6;

       u32 ctl1_enbl   :1;     /* D2 controller 1 enable */
       u32 win1_enbl   :1;     /* D2 window 1 enable */
       u32 awin1_enbl  :1;     /* D2 alternate window 1 enable */