epson1356fb.h

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

	TV_FILT_FLICKER = 4
};

enum tv_format_t {
	TV_FMT_COMPOSITE = 0,
	TV_FMT_S_VIDEO
};


struct e1356fb_fix {
	int system;       // the number of a pre-packaged system
	phys_t regbase_phys; // phys start address of registers
	phys_t membase_phys; // phys start address of fb memory

	// Memory parameters
	int mem_speed;    // speed: 50, 60, 70, or 80 (nsec)
	int mem_type;     // mem type: EDO-2CAS, FPM-2CAS, EDO-2WE, FPM-2WE
	int mem_refresh;  // refresh rate in KHz
	int mem_smr;      // suspend mode refresh: CAS_BEFORE_RAS, SELF, or NONE
	// Clocks
	int busclk;       // BUSCLK frequency, in KHz
	int mclk;         // MCLK freq, in KHz, will either be BUSCLK or BUSCLK/2
	int clki;         // CLKI frequency, in KHz
	int clki2;        // CLKI2 frequency, in KHz

	int disp_type;    // LCD, TFT, CRT, PAL, or NTSC

	// TV Options
	u8  tv_filt;      // TV Filter mask, LUM, CHROM, and FLICKER
	int tv_fmt;       // TV output format, COMPOSITE or S_VIDEO
    
	// Panel (LCD,TFT) Options
	int panel_el;     // enable support for EL-type panels
	int panel_width;  // Panel data width: LCD: 4/8/16, TFT: 9/12/18
    
	// Misc
	int noaccel;
	int nopan;
#ifdef CONFIG_MTRR
	int nomtrr;
#endif
	int nohwcursor;
	int mmunalign;    // force unaligned returned VA in mmap()
	char fontname[40];

	char *mode_option;
};


typedef struct {
	int pixclk_d;     // Desired Pixel Clock, KHz
	int pixclk;       // Closest supported clock to desired clock, KHz
	int error;        // percent error between pixclock and pixclock_d
	int clksrc;       // equal to busclk, mclk, clki, or clki2, KHz
	int divisor;      // pixclk = clksrc/divisor, where divisor = 1,2,3, or 4
	u8  pixclk_bits;  // pixclock register value for above settings
} pixclock_info_t;


struct e1356fb_par {
	int width;
	int height;
	int width_virt;   // Width in pixels
	int height_virt;  // Height in lines
	int bpp;          // bits-per-pixel
	int Bpp;          // Bytes-per-pixel

	// Timing
	pixclock_info_t ipclk;
	int horiz_ndp;    // Horiz. Non-Display Period, pixels
	int vert_ndp;     // Vert. Non-Display Period, lines
	int hsync_pol;    // Polarity of horiz. sync signal (HRTC for CRT/TV,
	// FPLINE for TFT). 0=active lo, 1=active hi
	int hsync_start;  // Horiz. Sync Start position, pixels
	int hsync_width;  // Horiz. Sync Pulse width, pixels
	int hsync_freq;   // calculated horizontal sync frequency
	int vsync_pol;    // Polarity of vert. sync signal (VRTC for CRT/TV,
	// FPFRAME for TFT). 0=active lo, 1=active hi
	int vsync_start;  // Vert. Sync Start position, lines
	int vsync_width;  // Vert. Sync Pulse width, lines
	int vsync_freq;   // calculated vertical sync frequency

	int cmap_len;     // color-map length
};



struct fb_info_e1356 {
	struct fb_info fb_info;

	void *regbase_virt;
	unsigned long regbase_size;
	void *membase_virt;
	unsigned long fb_size;

	e1356_reg_t reg;

	void* putcs_buffer;
    
	int max_pixclock;   // Max supported pixel clock, KHz
	int open, mmaped;   // open count, is mmap'ed
	
	u8 chip_rev;
    
#ifdef CONFIG_MTRR
	int mtrr_idx;
#endif

#ifdef SHADOW_FRAME_BUFFER
	struct {
		void* fb;
		struct timer_list timer;
	} shadow;
#endif

	struct { unsigned red, green, blue, pad; } palette[256];
	struct display disp;

#if defined(FBCON_HAS_CFB16)
	u16 fbcon_cmap16[16];
#endif
    
	struct {
		int type;
		int state;
		int w,h,u;
		int x,y,redraw;
		unsigned long enable,disable;
		struct timer_list timer;
		spinlock_t lock; 
	} cursor;
 
	struct e1356fb_fix fix;
	struct e1356fb_par default_par;
	struct e1356fb_par current_par;
};


// The following are boot options for particular SED1356-based target systems

enum {
	SYS_NULL,
	SYS_PB1000,
	SYS_PB1500,
	SYS_SDU1356,
	SYS_CLIO1050,
	NUM_SYSTEMS // must be last
};

static struct {
	struct e1356fb_fix fix;
	struct e1356fb_par par;
} systems[NUM_SYSTEMS] = {

	/*
	 * NULL system to help us detect missing options
 	 * when the driver is compiled as a module.
	 */
	{
		{   // fix
			SYS_NULL,
		},
		{   // par
		}
	},

	/*
	 * Alchemy Pb1000 evaluation board, SED1356
	 */
	{
		{   // fix
			SYS_PB1000,
			0xE00000000, 0xE00200000,
			60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
			0, 0,   // BUSCLK and MCLK are calculated at run-time
			40000, 14318, // CLKI, CLKI2
#ifdef CONFIG_PB1000_CRT
			DISP_TYPE_CRT,
			0, 0, // TV Options
			0, 0, // Panel options
#elif defined (CONFIG_PB1000_NTSC)
			DISP_TYPE_NTSC,
			TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM,
			TV_FMT_COMPOSITE,
			0, 0, // Panel options
#elif defined (CONFIG_PB1000_TFT)
			DISP_TYPE_TFT,
			0, 0, // TV Options
			0, 12, // Panel options, EL panel?, data width?
#else
			DISP_TYPE_PAL,
			TV_FILT_FLICKER|TV_FILT_LUM|TV_FILT_CHROM,
			TV_FMT_COMPOSITE,
			0, 0, // Panel options
#endif
			0, 0,
#ifdef CONFIG_MTRR
			0,
#endif
			0,
			0,
			{0},
			"800x600@60"
		},
		{   // par
			0, 0, 800, 600, 8, 1,
			// timings will be set by modedb
			{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
			256
		}
	},

	/*
	 * Alchemy Pb1500 evaluation board, SED13806
	 */
	{
		{   // fix
			SYS_PB1500,
			0xE1B000000, 0xE1B200000,
			50, MEM_TYPE_EMBEDDED_SDRAM, 64, MEM_SMR_CBR,
			0, 0,   // BUSCLK and MCLK are calculated at run-time
			40000, 14318, // CLKI, CLKI2
#ifdef CONFIG_PB1500_CRT
			DISP_TYPE_CRT,
			0, 0, // TV Options
			0, 0, // Panel options
#else
			DISP_TYPE_TFT,
			0, 0, // TV Options
			0, 12, // Panel options, EL panel?, data width?
#endif
			0, 0,
#ifdef CONFIG_MTRR
			0,
#endif
			0,
			0,
			{0},
			"800x600@60"
		},
		{   // par
			0, 0, 800, 600, 8, 1,
			// timings will be set by modedb
			{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
			256
		}
	},

	/*
	 * Epson SDU1356B0C PCI eval card. These settings assume the
	 * card is configured for PCI, the MediaPlug is disabled,
	 * and the onboard clock synthesizer is at the power-up
	 * clock settings.
	 */
	{
		{   // fix
			SYS_SDU1356,
			0x0, 0x0,  // addresses obtained from PCI config space
			// FIXME: just guess for now
			60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
			33000, 0, 40000, 25175, // BUSCLK, MCLK, CLKI, CLKI2
			DISP_TYPE_CRT,
			0, 0,
			0, 0,
			0, 0,
#ifdef CONFIG_MTRR
			0,
#endif
			0,
			0,
			{0},
			"800x600@60"
		},
		{   // par
			0, 0, 1024, 768, 8, 1,
			// timings will be set by modedb
			{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
			256
		}
	},

	/*
	 * Vadem Clio 1050 - this is for the benefit of the Linux-VR project.
	 * FIXME: Most of these settings are just guesses, until I can get a
	 * Clio 1050 and dump the registers that WinCE has setup.
	 */
	{
		{   // fix
			SYS_CLIO1050,
			0x0a000000, 0x0a200000,
			60, MEM_TYPE_EDO_2CAS, 64, MEM_SMR_CBR,
			40000, 40000, 14318, 14318,
			DISP_TYPE_TFT,
			0, 0,
			0, 16,
			0, 0,
#ifdef CONFIG_MTRR
			0,
#endif
			0,
			0,
			{0},
			"640x480@85"
		},
		{   // par
			0, 0, 1024, 768, 16, 2,
			// timings will be set by modedb
			{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
			16
		}
	}
};