radeon.h

S3C44B0X下的LCD （framebuffer）驱动资料与相关代码

#define	PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT    0x0000000d
#define	PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT        0x0000000e
#define	PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT        0x0000000f


// PIXCLKS_CNTL
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK                 0x00000003L
#define PIXCLKS_CNTL__PIX2CLK_INVERT_MASK                  0x00000010L
#define PIXCLKS_CNTL__PIX2CLK_INVERT                       0x00000010L
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT_MASK              0x00000020L
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT                   0x00000020L
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb_MASK              0x00000040L
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb                   0x00000040L
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb_MASK          0x00000080L
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb               0x00000080L
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL_MASK               0x00000100L
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL                    0x00000100L
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb_MASK         0x00000800L
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb              0x00000800L
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb_MASK            0x00001000L
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb                 0x00001000L
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb_MASK      0x00002000L
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb           0x00002000L
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb_MASK          0x00004000L
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb               0x00004000L
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb_MASK          0x00008000L
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb               0x00008000L


// P2PLL_DIV_0
#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK                     0x000007ffL
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK            0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W                 0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK            0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R                 0x00008000L
#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK                   0x00070000L

// SCLK_CNTL_M6
#define SCLK_CNTL_M6__SCLK_SRC_SEL_MASK                    0x00000007L
#define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT_MASK             0x00000008L
#define SCLK_CNTL_M6__CP_MAX_DYN_STOP_LAT                  0x00000008L
#define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT_MASK            0x00000010L
#define SCLK_CNTL_M6__HDP_MAX_DYN_STOP_LAT                 0x00000010L
#define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT_MASK             0x00000020L
#define SCLK_CNTL_M6__TV_MAX_DYN_STOP_LAT                  0x00000020L
#define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT_MASK             0x00000040L
#define SCLK_CNTL_M6__E2_MAX_DYN_STOP_LAT                  0x00000040L
#define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT_MASK             0x00000080L
#define SCLK_CNTL_M6__SE_MAX_DYN_STOP_LAT                  0x00000080L
#define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT_MASK           0x00000100L
#define SCLK_CNTL_M6__IDCT_MAX_DYN_STOP_LAT                0x00000100L
#define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT_MASK            0x00000200L
#define SCLK_CNTL_M6__VIP_MAX_DYN_STOP_LAT                 0x00000200L
#define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT_MASK             0x00000400L
#define SCLK_CNTL_M6__RE_MAX_DYN_STOP_LAT                  0x00000400L
#define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT_MASK             0x00000800L
#define SCLK_CNTL_M6__PB_MAX_DYN_STOP_LAT                  0x00000800L
#define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT_MASK            0x00001000L
#define SCLK_CNTL_M6__TAM_MAX_DYN_STOP_LAT                 0x00001000L
#define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT_MASK            0x00002000L
#define SCLK_CNTL_M6__TDM_MAX_DYN_STOP_LAT                 0x00002000L
#define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT_MASK             0x00004000L
#define SCLK_CNTL_M6__RB_MAX_DYN_STOP_LAT                  0x00004000L
#define SCLK_CNTL_M6__FORCE_DISP2_MASK                     0x00008000L
#define SCLK_CNTL_M6__FORCE_DISP2                          0x00008000L
#define SCLK_CNTL_M6__FORCE_CP_MASK                        0x00010000L
#define SCLK_CNTL_M6__FORCE_CP                             0x00010000L
#define SCLK_CNTL_M6__FORCE_HDP_MASK                       0x00020000L
#define SCLK_CNTL_M6__FORCE_HDP                            0x00020000L
#define SCLK_CNTL_M6__FORCE_DISP1_MASK                     0x00040000L
#define SCLK_CNTL_M6__FORCE_DISP1                          0x00040000L
#define SCLK_CNTL_M6__FORCE_TOP_MASK                       0x00080000L
#define SCLK_CNTL_M6__FORCE_TOP                            0x00080000L
#define SCLK_CNTL_M6__FORCE_E2_MASK                        0x00100000L
#define SCLK_CNTL_M6__FORCE_E2                             0x00100000L
#define SCLK_CNTL_M6__FORCE_SE_MASK                        0x00200000L
#define SCLK_CNTL_M6__FORCE_SE                             0x00200000L
#define SCLK_CNTL_M6__FORCE_IDCT_MASK                      0x00400000L
#define SCLK_CNTL_M6__FORCE_IDCT                           0x00400000L
#define SCLK_CNTL_M6__FORCE_VIP_MASK                       0x00800000L
#define SCLK_CNTL_M6__FORCE_VIP                            0x00800000L
#define SCLK_CNTL_M6__FORCE_RE_MASK                        0x01000000L
#define SCLK_CNTL_M6__FORCE_RE                             0x01000000L
#define SCLK_CNTL_M6__FORCE_PB_MASK                        0x02000000L
#define SCLK_CNTL_M6__FORCE_PB                             0x02000000L
#define SCLK_CNTL_M6__FORCE_TAM_MASK                       0x04000000L
#define SCLK_CNTL_M6__FORCE_TAM                            0x04000000L
#define SCLK_CNTL_M6__FORCE_TDM_MASK                       0x08000000L
#define SCLK_CNTL_M6__FORCE_TDM                            0x08000000L
#define SCLK_CNTL_M6__FORCE_RB_MASK                        0x10000000L
#define SCLK_CNTL_M6__FORCE_RB                             0x10000000L
#define SCLK_CNTL_M6__FORCE_TV_SCLK_MASK                   0x20000000L
#define SCLK_CNTL_M6__FORCE_TV_SCLK                        0x20000000L
#define SCLK_CNTL_M6__FORCE_SUBPIC_MASK                    0x40000000L
#define SCLK_CNTL_M6__FORCE_SUBPIC                         0x40000000L
#define SCLK_CNTL_M6__FORCE_OV0_MASK                       0x80000000L
#define SCLK_CNTL_M6__FORCE_OV0                            0x80000000L

// SCLK_MORE_CNTL
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT_MASK     0x00000001L
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT          0x00000001L
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT_MASK       0x00000002L
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT            0x00000002L
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT_MASK      0x00000004L
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT           0x00000004L
#define SCLK_MORE_CNTL__FORCE_DISPREGS_MASK                0x00000100L
#define SCLK_MORE_CNTL__FORCE_DISPREGS                     0x00000100L
#define SCLK_MORE_CNTL__FORCE_MC_GUI_MASK                  0x00000200L
#define SCLK_MORE_CNTL__FORCE_MC_GUI                       0x00000200L
#define SCLK_MORE_CNTL__FORCE_MC_HOST_MASK                 0x00000400L
#define SCLK_MORE_CNTL__FORCE_MC_HOST                      0x00000400L
#define SCLK_MORE_CNTL__STOP_SCLK_EN_MASK                  0x00001000L
#define SCLK_MORE_CNTL__STOP_SCLK_EN                       0x00001000L
#define SCLK_MORE_CNTL__STOP_SCLK_A_MASK                   0x00002000L
#define SCLK_MORE_CNTL__STOP_SCLK_A                        0x00002000L
#define SCLK_MORE_CNTL__STOP_SCLK_B_MASK                   0x00004000L
#define SCLK_MORE_CNTL__STOP_SCLK_B                        0x00004000L
#define SCLK_MORE_CNTL__STOP_SCLK_C_MASK                   0x00008000L
#define SCLK_MORE_CNTL__STOP_SCLK_C                        0x00008000L
#define SCLK_MORE_CNTL__HALF_SPEED_SCLK_MASK               0x00010000L
#define SCLK_MORE_CNTL__HALF_SPEED_SCLK                    0x00010000L
#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP_MASK            0x00020000L
#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP                 0x00020000L
#define SCLK_MORE_CNTL__TVFB_SOFT_RESET_MASK               0x00040000L
#define SCLK_MORE_CNTL__TVFB_SOFT_RESET                    0x00040000L
#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC_MASK             0x00080000L
#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC                  0x00080000L
#define SCLK_MORE_CNTL__VOLTAGE_DELAY_SEL_MASK             0x00300000L
#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK_MASK          0x00400000L
#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK               0x00400000L
#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK_MASK            0x00800000L
#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK                 0x00800000L
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK                 0xff000000L

// MCLK_CNTL_M6
#define MCLK_CNTL_M6__MCLKA_SRC_SEL_MASK                   0x00000007L
#define MCLK_CNTL_M6__YCLKA_SRC_SEL_MASK                   0x00000070L
#define MCLK_CNTL_M6__MCLKB_SRC_SEL_MASK                   0x00000700L
#define MCLK_CNTL_M6__YCLKB_SRC_SEL_MASK                   0x00007000L
#define MCLK_CNTL_M6__FORCE_MCLKA_MASK                     0x00010000L
#define MCLK_CNTL_M6__FORCE_MCLKA                          0x00010000L
#define MCLK_CNTL_M6__FORCE_MCLKB_MASK                     0x00020000L
#define MCLK_CNTL_M6__FORCE_MCLKB                          0x00020000L
#define MCLK_CNTL_M6__FORCE_YCLKA_MASK                     0x00040000L
#define MCLK_CNTL_M6__FORCE_YCLKA                          0x00040000L
#define MCLK_CNTL_M6__FORCE_YCLKB_MASK                     0x00080000L
#define MCLK_CNTL_M6__FORCE_YCLKB                          0x00080000L
#define MCLK_CNTL_M6__FORCE_MC_MASK                        0x00100000L
#define MCLK_CNTL_M6__FORCE_MC                             0x00100000L
#define MCLK_CNTL_M6__FORCE_AIC_MASK                       0x00200000L
#define MCLK_CNTL_M6__FORCE_AIC                            0x00200000L
#define MCLK_CNTL_M6__MRDCKA0_SOUTSEL_MASK                 0x03000000L
#define MCLK_CNTL_M6__MRDCKA1_SOUTSEL_MASK                 0x0c000000L
#define MCLK_CNTL_M6__MRDCKB0_SOUTSEL_MASK                 0x30000000L
#define MCLK_CNTL_M6__MRDCKB1_SOUTSEL_MASK                 0xc0000000L

// MCLK_MISC
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK         0x00000003L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK             0x00000004L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL                  0x00000004L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK              0x00000008L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL                   0x00000008L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK         0x00000010L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN              0x00000010L
#define MCLK_MISC__DLL_READY_LAT_MASK                      0x00000100L
#define MCLK_MISC__DLL_READY_LAT                           0x00000100L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK           0x00001000L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT                0x00001000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK           0x00002000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT                0x00002000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK                 0x00004000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE                      0x00004000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK                 0x00008000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE                      0x00008000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK                  0x00010000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN                       0x00010000L
#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK                   0x00020000L
#define MCLK_MISC__CLK_OR_COUNT_SEL                        0x00020000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK        0x00040000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND             0x00040000L
#define MCLK_MISC__CGM_SPARE_RD_MASK                       0x00300000L
#define MCLK_MISC__CGM_SPARE_A_RD_MASK                     0x00c00000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK                   0x01000000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN                        0x01000000L
#define MCLK_MISC__CGM_SPARE_A_MASK                        0x0e000000L

// VCLK_ECP_CNTL
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK                   0x00000003L
#define VCLK_ECP_CNTL__VCLK_INVERT_MASK                    0x00000010L
#define VCLK_ECP_CNTL__VCLK_INVERT                         0x00000010L
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT_MASK              0x00000020L
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT                   0x00000020L
#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb_MASK              0x00000040L
#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb                   0x00000040L
#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb_MASK          0x00000080L
#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb               0x00000080L
#define VCLK_ECP_CNTL__ECP_DIV_MASK                        0x00000300L
#define VCLK_ECP_CNTL__ECP_FORCE_ON_MASK                   0x00040000L
#define VCLK_ECP_CNTL__ECP_FORCE_ON                        0x00040000L
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON_MASK                0x00080000L
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON                     0x00080000L

// PLL_PWRMGT_CNTL
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK                 0x00000001L
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF                      0x00000001L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK                 0x00000002L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF                      0x00000002L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK                 0x00000004L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF                      0x00000004L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK                0x00000008L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF                     0x00000008L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK                0x00000010L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF                     0x00000010L
#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK          0x000001e0L
#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK              0x00000600L
#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK              0x00001800L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK                  0x00002000L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL                       0x00002000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK          0x00004000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND               0x00004000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK          0x00008000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND               0x00008000L
#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK                    0x00010000L
#define PLL_PWRMGT_CNTL__MOBILE_SU                         0x00010000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK             0x00020000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK                  0x00020000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK             0x00040000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK                  0x00040000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK           0x00080000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE                0x00080000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK           0x00100000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE                0x00100000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD_MASK          0x00200000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD               0x00200000L
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK                 0xff000000L

// CLK_PWRMGT_CNTL_M6
#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF_MASK           0x00000001L
#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF                0x00000001L
#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF_MASK           0x00000002L
#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF                0x00000002L
#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF_MASK           0x00000004L
#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_O