📄 radeon.h
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#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002#define GMC_SRC_CLIP_DEFAULT 0x00000000#define GMC_SRC_CLIP_LEAVE 0x00000004#define GMC_DST_CLIP_DEFAULT 0x00000000#define GMC_DST_CLIP_LEAVE 0x00000008#define GMC_BRUSH_8x8MONO 0x00000000#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010#define GMC_BRUSH_8x1MONO 0x00000020#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030#define GMC_BRUSH_1x8MONO 0x00000040#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050#define GMC_BRUSH_32x1MONO 0x00000060#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070#define GMC_BRUSH_32x32MONO 0x00000080#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090#define GMC_BRUSH_8x8COLOR 0x000000a0#define GMC_BRUSH_8x1COLOR 0x000000b0#define GMC_BRUSH_1x8COLOR 0x000000c0#define GMC_BRUSH_SOLID_COLOR 0x000000d0#define GMC_DST_8BPP 0x00000200#define GMC_DST_15BPP 0x00000300#define GMC_DST_16BPP 0x00000400#define GMC_DST_24BPP 0x00000500#define GMC_DST_32BPP 0x00000600#define GMC_DST_8BPP_RGB332 0x00000700#define GMC_DST_8BPP_Y8 0x00000800#define GMC_DST_8BPP_RGB8 0x00000900#define GMC_DST_16BPP_VYUY422 0x00000b00#define GMC_DST_16BPP_YVYU422 0x00000c00#define GMC_DST_32BPP_AYUV444 0x00000e00#define GMC_DST_16BPP_ARGB4444 0x00000f00#define GMC_SRC_MONO 0x00000000#define GMC_SRC_MONO_LBKGD 0x00001000#define GMC_SRC_DSTCOLOR 0x00003000#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000#define GMC_DP_CONVERSION_TEMP_9300 0x00008000#define GMC_DP_CONVERSION_TEMP_6500 0x00000000#define GMC_DP_SRC_RECT 0x02000000#define GMC_DP_SRC_HOST 0x03000000#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000#define GMC_3D_FCN_EN_CLR 0x00000000#define GMC_3D_FCN_EN_SET 0x08000000#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000#define GMC_AUX_CLIP_LEAVE 0x00000000#define GMC_AUX_CLIP_CLEAR 0x20000000#define GMC_WRITE_MASK_LEAVE 0x00000000#define GMC_WRITE_MASK_SET 0x40000000#define GMC_CLR_CMP_CNTL_DIS (1 << 28)#define GMC_SRC_DATATYPE_COLOR (3 << 12)#define ROP3_S 0x00cc0000#define ROP3_SRCCOPY 0x00cc0000#define ROP3_P 0x00f00000#define ROP3_PATCOPY 0x00f00000#define DP_SRC_SOURCE_MASK (7 << 24)#define GMC_BRUSH_NONE (15 << 4)#define DP_SRC_SOURCE_MEMORY (2 << 24)#define GMC_BRUSH_SOLIDCOLOR 0x000000d0/* DP_MIX bit constants */#define DP_SRC_RECT 0x00000200#define DP_SRC_HOST 0x00000300#define DP_SRC_HOST_BYTEALIGN 0x00000400/* MPLL_CNTL bit constants */#define MPLL_RESET 0x00000001/* MDLL_RDCKA bit constants */#define MRDCKA0_SLEEP 0x00000001#define MRDCKA0_RESET 0x00000002#define MRDCKA1_SLEEP 0x00010000#define MRDCKA1_RESET 0x00020000/* VCLK_ECP_CNTL constants */#define PIXCLK_ALWAYS_ONb 0x00000040#define PIXCLK_DAC_ALWAYS_ONb 0x00000080/* BUS_CNTL1 constants */#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26#define BUS_CNTL1_AGPCLK_VALID 0x80000000/* PLL_PWRMGT_CNTL constants */#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000/* TV_DAC_CNTL constants */#define TV_DAC_CNTL_BGSLEEP 0x00000040#define TV_DAC_CNTL_DETECT 0x00000010#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000#define TV_DAC_CNTL_BGADJ__SHIFT 16#define TV_DAC_CNTL_DACADJ__SHIFT 20#define TV_DAC_CNTL_RDACPD 0x01000000#define TV_DAC_CNTL_GDACPD 0x02000000#define TV_DAC_CNTL_BDACPD 0x04000000/* DISP_MISC_CNTL constants */#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)/* DISP_PWR_MAN constants */#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)/* masks */#define CONFIG_MEMSIZE_MASK 0x1f000000#define MEM_CFG_TYPE 0x40000000#define DST_OFFSET_MASK 0x003fffff#define DST_PITCH_MASK 0x3fc00000#define DEFAULT_TILE_MASK 0xc0000000#define PPLL_DIV_SEL_MASK 0x00000300#define PPLL_RESET 0x00000001#define PPLL_ATOMIC_UPDATE_EN 0x00010000#define PPLL_REF_DIV_MASK 0x000003ff#define PPLL_FB3_DIV_MASK 0x000007ff#define PPLL_POST3_DIV_MASK 0x00070000#define PPLL_ATOMIC_UPDATE_R 0x00008000#define PPLL_ATOMIC_UPDATE_W 0x00008000#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000#define GUI_ACTIVE 0x80000000#define MC_IND_INDEX 0x01F8#define MC_IND_DATA 0x01FC#define MEM_REFRESH_CNTL 0x0178// CLK_PIN_CNTL#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L#define CLK_PIN_CNTL__OSC_EN 0x00000001L#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L#define CLK_PIN_CNTL__CG_SPARE 0x00004000L#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L// CLK_PWRMGT_CNTL_M6#define CLK_PWRMGT_CNTL_M6__MPLL_PWRMGT_OFF__SHIFT 0x00000000#define CLK_PWRMGT_CNTL_M6__SPLL_PWRMGT_OFF__SHIFT 0x00000001#define CLK_PWRMGT_CNTL_M6__PPLL_PWRMGT_OFF__SHIFT 0x00000002#define CLK_PWRMGT_CNTL_M6__P2PLL_PWRMGT_OFF__SHIFT 0x00000003#define CLK_PWRMGT_CNTL_M6__MCLK_TURNOFF__SHIFT 0x00000004#define CLK_PWRMGT_CNTL_M6__SCLK_TURNOFF__SHIFT 0x00000005#define CLK_PWRMGT_CNTL_M6__PCLK_TURNOFF__SHIFT 0x00000006#define CLK_PWRMGT_CNTL_M6__P2CLK_TURNOFF__SHIFT 0x00000007#define CLK_PWRMGT_CNTL_M6__MC_CH_MODE__SHIFT 0x00000008#define CLK_PWRMGT_CNTL_M6__TEST_MODE__SHIFT 0x00000009#define CLK_PWRMGT_CNTL_M6__GLOBAL_PMAN_EN__SHIFT 0x0000000a#define CLK_PWRMGT_CNTL_M6__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c#define CLK_PWRMGT_CNTL_M6__ACTIVE_HILO_LAT__SHIFT 0x0000000d#define CLK_PWRMGT_CNTL_M6__DISP_DYN_STOP_LAT__SHIFT 0x0000000f#define CLK_PWRMGT_CNTL_M6__MC_BUSY__SHIFT 0x00000010#define CLK_PWRMGT_CNTL_M6__MC_INT_CNTL__SHIFT 0x00000011#define CLK_PWRMGT_CNTL_M6__MC_SWITCH__SHIFT 0x00000012#define CLK_PWRMGT_CNTL_M6__DLL_READY__SHIFT 0x00000013#define CLK_PWRMGT_CNTL_M6__DISP_PM__SHIFT 0x00000014#define CLK_PWRMGT_CNTL_M6__DYN_STOP_MODE__SHIFT 0x00000015#define CLK_PWRMGT_CNTL_M6__CG_NO1_DEBUG__SHIFT 0x00000018#define CLK_PWRMGT_CNTL_M6__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e#define CLK_PWRMGT_CNTL_M6__TVCLK_TURNOFF__SHIFT 0x0000001f// P2PLL_CNTL#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L#define P2PLL_CNTL__P2PLL_RESET 0x00000001L#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L// PIXCLKS_CNTL#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c⌨️ 快捷键说明
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