📄 radeon.h
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/* DSTCACHE_CTLSTAT bit constants */#define RB2D_DC_FLUSH (3 << 0)#define RB2D_DC_FLUSH_ALL 0xf#define RB2D_DC_BUSY (1 << 31)/* CRTC_GEN_CNTL bit constants */#define CRTC_DBL_SCAN_EN 0x00000001#define CRTC_CUR_EN 0x00010000#define CRTC_INTERLACE_EN (1 << 1)#define CRTC_BYPASS_LUT_EN (1 << 14)#define CRTC_EXT_DISP_EN (1 << 24)#define CRTC_EN (1 << 25)#define CRTC_DISP_REQ_EN_B (1 << 26)/* CRTC_STATUS bit constants */#define CRTC_VBLANK 0x00000001/* CRTC2_GEN_CNTL bit constants */#define CRT2_ON (1 << 7)#define CRTC2_DISPLAY_DIS (1 << 23)#define CRTC2_EN (1 << 25)#define CRTC2_DISP_REQ_EN_B (1 << 26)/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */#define CUR_LOCK 0x80000000/* FP bit constants */#define FP_CRTC_H_TOTAL_MASK 0x000003ff#define FP_CRTC_H_DISP_MASK 0x01ff0000#define FP_CRTC_V_TOTAL_MASK 0x00000fff#define FP_CRTC_V_DISP_MASK 0x0fff0000#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8#define FP_H_SYNC_WID_MASK 0x003f0000#define FP_V_SYNC_STRT_MASK 0x00000fff#define FP_V_SYNC_WID_MASK 0x001f0000#define FP_CRTC_H_TOTAL_SHIFT 0x00000000#define FP_CRTC_H_DISP_SHIFT 0x00000010#define FP_CRTC_V_TOTAL_SHIFT 0x00000000#define FP_CRTC_V_DISP_SHIFT 0x00000010#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003#define FP_H_SYNC_WID_SHIFT 0x00000010#define FP_V_SYNC_STRT_SHIFT 0x00000000#define FP_V_SYNC_WID_SHIFT 0x00000010/* FP_GEN_CNTL bit constants */#define FP_FPON (1 << 0)#define FP_TMDS_EN (1 << 2)#define FP_EN_TMDS (1 << 7)#define FP_DETECT_SENSE (1 << 8)#define FP_SEL_CRTC2 (1 << 13)#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)#define FP_CRTC_USE_SHADOW_VEND (1 << 18)#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)#define FP_DFP_SYNC_SEL (1 << 21)#define FP_CRTC_LOCK_8DOT (1 << 22)#define FP_CRT_SYNC_SEL (1 << 23)#define FP_USE_SHADOW_EN (1 << 24)#define FP_CRT_SYNC_ALT (1 << 26)/* LVDS_GEN_CNTL bit constants */#define LVDS_ON (1 << 0)#define LVDS_DISPLAY_DIS (1 << 1)#define LVDS_PANEL_TYPE (1 << 2)#define LVDS_PANEL_FORMAT (1 << 3)#define LVDS_EN (1 << 7)#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00#define LVDS_BL_MOD_LEVEL_SHIFT 8#define LVDS_BL_MOD_EN (1 << 16)#define LVDS_DIGON (1 << 18)#define LVDS_BLON (1 << 19)#define LVDS_SEL_CRTC2 (1 << 23)#define LVDS_STATE_MASK \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | \ LVDS_EN | LVDS_DIGON | LVDS_BLON)/* LVDS_PLL_CNTL bit constatns */#define HSYNC_DELAY_SHIFT 0x1c#define HSYNC_DELAY_MASK (0xf << 0x1c)/* TMDS_TRANSMITTER_CNTL bit constants */#define TMDS_PLL_EN (1 << 0)#define TMDS_PLLRST (1 << 1)#define TMDS_RAN_PAT_RST (1 << 7)#define TMDS_ICHCSEL (1 << 28)/* FP_HORZ_STRETCH bit constants */#define HORZ_STRETCH_RATIO_MASK 0xffff#define HORZ_STRETCH_RATIO_MAX 4096#define HORZ_PANEL_SIZE (0x1ff << 16)#define HORZ_PANEL_SHIFT 16#define HORZ_STRETCH_PIXREP (0 << 25)#define HORZ_STRETCH_BLEND (1 << 26)#define HORZ_STRETCH_ENABLE (1 << 25)#define HORZ_AUTO_RATIO (1 << 27)#define HORZ_FP_LOOP_STRETCH (0x7 << 28)#define HORZ_AUTO_RATIO_INC (1 << 31)/* FP_VERT_STRETCH bit constants */#define VERT_STRETCH_RATIO_MASK 0xfff#define VERT_STRETCH_RATIO_MAX 4096#define VERT_PANEL_SIZE (0xfff << 12)#define VERT_PANEL_SHIFT 12#define VERT_STRETCH_LINREP (0 << 26)#define VERT_STRETCH_BLEND (1 << 26)#define VERT_STRETCH_ENABLE (1 << 25)#define VERT_AUTO_RATIO_EN (1 << 27)#define VERT_FP_LOOP_STRETCH (0x7 << 28)#define VERT_STRETCH_RESERVED 0xf1000000/* DAC_CNTL bit constants */ #define DAC_8BIT_EN 0x00000100#define DAC_4BPP_PIX_ORDER 0x00000200#define DAC_CRC_EN 0x00080000#define DAC_MASK_ALL (0xff << 24)#define DAC_EXPAND_MODE (1 << 14)#define DAC_VGA_ADR_EN (1 << 13)#define DAC_RANGE_CNTL (3 << 0)#define DAC_BLANKING (1 << 2)#define DAC_CMP_EN (1 << 3)/* DAC_CNTL2 bit constants */ #define DAC2_CMP_EN (1 << 7)#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)/* GEN_RESET_CNTL bit constants */#define SOFT_RESET_GUI 0x00000001#define SOFT_RESET_VCLK 0x00000100#define SOFT_RESET_PCLK 0x00000200#define SOFT_RESET_ECP 0x00000400#define SOFT_RESET_DISPENG_XCLK 0x00000800/* MEM_CNTL bit constants */#define MEM_CTLR_STATUS_IDLE 0x00000000#define MEM_CTLR_STATUS_BUSY 0x00100000#define MEM_SEQNCR_STATUS_IDLE 0x00000000#define MEM_SEQNCR_STATUS_BUSY 0x00200000#define MEM_ARBITER_STATUS_IDLE 0x00000000#define MEM_ARBITER_STATUS_BUSY 0x00400000#define MEM_REQ_UNLOCK 0x00000000#define MEM_REQ_LOCK 0x00800000/* RBBM_SOFT_RESET bit constants */#define SOFT_RESET_CP (1 << 0)#define SOFT_RESET_HI (1 << 1)#define SOFT_RESET_SE (1 << 2)#define SOFT_RESET_RE (1 << 3)#define SOFT_RESET_PP (1 << 4)#define SOFT_RESET_E2 (1 << 5)#define SOFT_RESET_RB (1 << 6)#define SOFT_RESET_HDP (1 << 7)/* HOST_PATH_CNTL bit constants */#define HDP_SOFT_RESET (1 << 26)/* SURFACE_CNTL bit consants */#define SURF_TRANSLATION_DIS (1 << 8)#define NONSURF_AP0_SWP_16BPP (1 << 20)#define NONSURF_AP0_SWP_32BPP (1 << 21)#define NONSURF_AP1_SWP_16BPP (1 << 22)#define NONSURF_AP1_SWP_32BPP (1 << 23)/* DEFAULT_SC_BOTTOM_RIGHT bit constants */#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)/* MM_INDEX bit constants */#define MM_APER 0x80000000/* CLR_CMP_CNTL bit constants */#define COMPARE_SRC_FALSE 0x00000000#define COMPARE_SRC_TRUE 0x00000001#define COMPARE_SRC_NOT_EQUAL 0x00000004#define COMPARE_SRC_EQUAL 0x00000005#define COMPARE_SRC_EQUAL_FLIP 0x00000007#define COMPARE_DST_FALSE 0x00000000#define COMPARE_DST_TRUE 0x00000100#define COMPARE_DST_NOT_EQUAL 0x00000400#define COMPARE_DST_EQUAL 0x00000500#define COMPARE_DESTINATION 0x00000000#define COMPARE_SOURCE 0x01000000#define COMPARE_SRC_AND_DST 0x02000000/* DP_CNTL bit constants */#define DST_X_RIGHT_TO_LEFT 0x00000000#define DST_X_LEFT_TO_RIGHT 0x00000001#define DST_Y_BOTTOM_TO_TOP 0x00000000#define DST_Y_TOP_TO_BOTTOM 0x00000002#define DST_X_MAJOR 0x00000000#define DST_Y_MAJOR 0x00000004#define DST_X_TILE 0x00000008#define DST_Y_TILE 0x00000010#define DST_LAST_PEL 0x00000020#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080#define DST_BRES_SIGN 0x00000100#define DST_HOST_BIG_ENDIAN_EN 0x00000200#define DST_POLYLINE_NONLAST 0x00008000#define DST_RASTER_STALL 0x00010000#define DST_POLY_EDGE 0x00040000/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */#define DST_X_MAJOR_S 0x00000000#define DST_Y_MAJOR_S 0x00000001#define DST_Y_BOTTOM_TO_TOP_S 0x00000000#define DST_Y_TOP_TO_BOTTOM_S 0x00008000#define DST_X_RIGHT_TO_LEFT_S 0x00000000#define DST_X_LEFT_TO_RIGHT_S 0x80000000/* DP_DATATYPE bit constants */#define DST_8BPP 0x00000002#define DST_15BPP 0x00000003#define DST_16BPP 0x00000004#define DST_24BPP 0x00000005#define DST_32BPP 0x00000006#define DST_8BPP_RGB332 0x00000007#define DST_8BPP_Y8 0x00000008#define DST_8BPP_RGB8 0x00000009#define DST_16BPP_VYUY422 0x0000000b#define DST_16BPP_YVYU422 0x0000000c#define DST_32BPP_AYUV444 0x0000000e#define DST_16BPP_ARGB4444 0x0000000f#define BRUSH_SOLIDCOLOR 0x00000d00#define SRC_MONO 0x00000000#define SRC_MONO_LBKGD 0x00010000#define SRC_DSTCOLOR 0x00030000#define BYTE_ORDER_MSB_TO_LSB 0x00000000#define BYTE_ORDER_LSB_TO_MSB 0x40000000#define DP_CONVERSION_TEMP 0x80000000#define HOST_BIG_ENDIAN_EN (1 << 29)/* DP_GUI_MASTER_CNTL bit constants */⌨️ 快捷键说明
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