app_vect.c

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

/*
*********************************************************************************************************
*                                              EXAMPLE CODE
*
*                          (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
*
*               All rights reserved.  Protected by international copyright laws.
*               Knowledge of the source code may NOT be used to develop a similar product.
*               Please help us continue to provide the Embedded community with the finest
*               software available.  Your honesty is greatly appreciated.
*********************************************************************************************************
*/

/*
*********************************************************************************************************
*
*                                         EXCEPTION VECTORS
*
*                                       Luminary Micro LM3S6965
*                                              with the
*                             Luminary Micro LM3S6965 ENET Development Kit
*
* Filename      : app_vect.c
* Version       : V1.00
* Programmer(s) : Brian Nagel
*********************************************************************************************************
*/

#include <includes.h>


#pragma language=extended

/*
*********************************************************************************************************
*                                              DATA TYPES
*********************************************************************************************************
*/

typedef  void  (*intfunc)(void);


typedef  union {
    intfunc  __fun;
    void    *__ptr;
} INTVECT_ELEM;

/*
*********************************************************************************************************
*                                              PROTOTYPES
*********************************************************************************************************
*/

       void  __program_start     (void);

static void  App_NMI_ISR         (void);
static void  App_Fault_ISR       (void);


/*
*********************************************************************************************************
*                                  Exception / Interrupt Vector Table
*********************************************************************************************************
*/

#pragma segment = "CSTACK"

#pragma location = "INTVEC"
__root  const  INTVECT_ELEM  AppVectTbl[] = {
    { .__ptr = __sfe("CSTACK")},        /*  0, SP start value.                                         */
    __program_start,                    /*  1, PC start value.                                         */
    App_NMI_ISR,                        /*  2, NMI                                                     */
    App_Fault_ISR,                      /*  3, Hard Fault                                              */
    0,                                  /*  4, Memory Management                                       */
    0,                                  /*  5, Bus Fault                                               */
    0,                                  /*  6, Usage Fault                                             */
    0,                                  /*  7, Reserved                                                */
    0,                                  /*  8, Reserved                                                */
    0,                                  /*  9, Reserved                                                */
    0,                                  /* 10, Reserved                                                */
    0,                                  /* 11, SVCall                                                  */
    0,                                  /* 12, Debug Monitor                                           */
    0,                                  /* 13, Reserved                                                */
    OSPendSV,                           /* 14, PendSV Handler                                          */
    Tmr_TickISR_Handler,                /* 15, uC/OS-II Tick ISR Handler                               */
    0,                                  /* 16, INTISR[  0], GPIOA                                      */
    0,                                  /* 17, INTISR[  1]  GPIOB                                      */
    0,                                  /* 18, INTISR[  2]  GPIOC                                      */
    0,                                  /* 19, INTISR[  3]  GPIOD                                      */
    0,                                  /* 20, INTISR[  4]  GPIOE                                      */
    0,                                  /* 21, INTISR[  5]  UART0                                      */
    0,                                  /* 22, INTISR[  6]  UART1                                      */
    0,                                  /* 23, INTISR[  7]  SSI0                                       */
    0,                                  /* 24, INTISR[  8]  I2C0                                       */
    0,                                  /* 25, INTISR[  9]  PWM Fault                                  */
    0,                                  /* 26, INTISR[ 10]  PWM Generator 0                            */
    0,                                  /* 27, INTISR[ 11]  PWM Generator 1                            */
    0,                                  /* 28, INTISR[ 12]  PWM Generator 2                            */
    0,                                  /* 29, INTISR[ 13]  QEI 0                                      */
    0,                                  /* 30, INTISR[ 14]  ADC Sequence 0                             */
    0,                                  /* 31, INTISR[ 15]  ADC Sequence 1                             */
    0,                                  /* 32, INTISR[ 16]  ADC Sequence 2                             */
    0,                                  /* 33, INTISR[ 17]  ADC Sequence 3                             */
    0,                                  /* 34, INTISR[ 18]  Watchdog Timer                             */
    0,                                  /* 35, INTISR[ 19]  Timer0 A                                   */
    0,                                  /* 36, INTISR[ 20]  Timer0 B                                   */
    0,                                  /* 37, INTISR[ 21]  Timer1 A                                   */
    0,                                  /* 38, INTISR[ 22]  Timer1 B                                   */
    0,                                  /* 39, INTISR[ 23]  Timer2 A                                   */
    0,                                  /* 40, INTISR[ 24]  Timer2 B                                   */
    0,                                  /* 41, INTISR[ 25]  Analog Comparator 0 (S/F)                  */
    0,                                  /* 42, INTISR[ 26]  Analog Comparator 1 (S/F)                  */
    0,                                  /* 43, INTISR[ 27]  Analog Comparator 2 (S/F)                  */
    0,                                  /* 44, INTISR[ 28]  System Control                             */
    0,                                  /* 45, INTISR[ 29]  Flash Control                              */
    0,                                  /* 46, INTISR[ 30]  GPIO Port F                                */
    0,                                  /* 47, INTISR[ 31]  GPIO Port G                                */
    0,                                  /* 48, INTISR[ 32]  GPIO Port H                                */
    0,                                  /* 49, INTISR[ 33]  UART2                                      */
    0,                                  /* 50, INTISR[ 34]  SSI1                                       */
    0,                                  /* 51, INTISR[ 35]  Timer3 A                                   */
    0,                                  /* 52, INTISR[ 36]  Timer3 B                                   */
    0,                                  /* 53, INTISR[ 37]  I2C1 Master and Slave                      */
    0,                                  /* 54, INTISR[ 38]  QEI1                                       */
    0,                                  /* 55, INTISR[ 39]  CAN0                                       */
    0,                                  /* 56, INTISR[ 40]  CAN1                                       */
    0,                                  /* 57, INTISR[ 41]  CAN2                                       */
    0,                                  /* 58, INTISR[ 42]  Ethernet MAC                               */
    0,                                  /* 59, INTISR[ 43]  Power Island                               */
    0,                                  /* 60, INTISR[ 44]  Reserved                                   */
    0,                                  /* 61, INTISR[ 45]  Reserved                                   */
    0,                                  /* 62, INTISR[ 46]  Reserved                                   */
    0                                   /* 63, INTISR[ 47]  Reserved                                   */
};


/*
*********************************************************************************************************
*                                        NMI Exception Handler
*********************************************************************************************************
*/

static  void  App_NMI_ISR (void) @ "ICODE"
{
    while (1) {
        ;
    }
}

/*
*********************************************************************************************************
*                                       FAULT Exception Handler
*********************************************************************************************************
*/

static  void  App_Fault_ISR (void) @ "ICODE"
{
    while (1) {
        ;
    }
}