📄 net_phy.c
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK PHYSICAL LAYER
*
* LuminaryMicro LM3Snnnn Internal PHY
*
* Filename : net_phy.c
* Version : V1.90
* Programmer(s) : BAN
*********************************************************************************************************
* Note(s) : (1) Supports internal PHY for EMAC section of LuminaryMicro's LM3Snnnn microcontroller.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#include <net.h>
#include <net_phy_def.h>
#include <net_phy.h>
/*
*********************************************************************************************************
* LM3SNNNN PHY REGISTER DEFINITIONS
*********************************************************************************************************
*/
#define PHY_MR00 0x00 /* Control */
#define PHY_MR01 0x01 /* Status */
#define PHY_MR02 0x02 /* Identifier 1 */
#define PHY_MR03 0x03 /* Identifier 2 */
#define PHY_MR04 0x04 /* Auto-negotiation advertisement */
#define PHY_MR05 0x05 /* Auto-negotiation link partner base page ability */
#define PHY_MR06 0x06 /* Auto-negotiation expansion */
#define PHY_MR16 0x10 /* Vendor-specific */
#define PHY_MR17 0x11 /* Interrupt control/status */
#define PHY_MR18 0x12 /* Diagnostic register */
#define PHY_MR19 0x13 /* Transceiver controll */
#define PHY_MR23 0x17 /* LED configuration */
#define PHY_MR24 0x18 /* MDI/MDIX control register */
/*
*********************************************************************************************************
* LM3SNNNN PHY REGISTER BIT DEFINITIONS
*********************************************************************************************************
*/
/* PHY Control Register bit definitions */
#define PHY_MR00_RESET DEF_BIT_15
#define PHY_MR00_LOOPBK DEF_BIT_14
#define PHY_MR00_SPEEDSL DEF_BIT_13
#define PHY_MR00_ANEGEN DEF_BIT_12
#define PHY_MR00_PWRDN DEF_BIT_11
#define PHY_MR00_ISO DEF_BIT_10
#define PHY_MR00_RANEG DEF_BIT_09
#define PHY_MR00_DUPLEX DEF_BIT_08
#define PHY_MR00_COLT DEF_BIT_07
/* PHY Status Register bit definitions */
#define PHY_MR01_100T4 DEF_BIT_15
#define PHY_MR01_100X_F DEF_BIT_14
#define PHY_MR01_100X_H DEF_BIT_13
#define PHY_MR01_10T_F DEF_BIT_12
#define PHY_MR01_10T_H DEF_BIT_11
#define PHY_MR01_100T2_F DEF_BIT_10
#define PHY_MR01_100T2_H DEF_BIT_09
#define PHY_MR01_MFPS DEF_BIT_06
#define PHY_MR01_ANEGC DEF_BIT_05
#define PHY_MR01_RFAULT DEF_BIT_04
#define PHY_MR01_ANEGA DEF_BIT_03
#define PHY_MR01_LINK DEF_BIT_02
#define PHY_MR01_JAB DEF_BIT_01
#define PHY_MR01_EXTD DEF_BIT_00
#define PHY_MR04_NP DEF_BIT_15
#define PHY_MR04_RF DEF_BIT_13
#define PHY_MR04_A7 DEF_BIT_12
#define PHY_MR04_A4 DEF_BIT_09
#define PHY_MR04_A3 DEF_BIT_08
#define PHY_MR04_A2 DEF_BIT_07
#define PHY_MR04_A1 DEF_BIT_06
#define PHY_MR04_A0 DEF_BIT_05
#define PHY_MR04_S 0x000F
#define PHY_MR05_NP DEF_BIT_15
#define PHY_MR05_ACK DEF_BIT_14
#define PHY_MR05_RF DEF_BIT_13
#define PHY_MR05_A 0x1FC0
#define PHY_MR05_S 0x000F
#define PHY_MR06_PDF DEF_BIT_04
#define PHY_MR06_LPNPA DEF_BIT_03
#define PHY_MR06_NPA DEF_BIT_02
#define PHY_MR06_PRX DEF_BIT_01
#define PHY_MR06_LPANEGA DEF_BIT_00
#define PHY_MR16_RPTR DEF_BIT_15
#define PHY_MR16_INPOL DEF_BIT_14
#define PHY_MR16_TXHIM DEF_BIT_12
#define PHY_MR16_SQEI DEF_BIT_11
#define PHY_MR16_NL10 DEF_BIT_10
#define PHY_MR16_APOL DEF_BIT_05
#define PHY_MR16_RSVPOL DEF_BIT_04
#define PHY_MR16_PCSBP DEF_BIT_01
#define PHY_MR16_RXCC DEF_BIT_00
#define PHY_MR17_JABBER_IE DEF_BIT_15
#define PHY_MR17_RXER_IE DEF_BIT_14
#define PHY_MR17_PRX_IE DEF_BIT_13
#define PHY_MR17_PDF_IE DEF_BIT_12
#define PHY_MR17_LPACK_IE DEF_BIT_11
#define PHY_MR17_LSCHG_IE DEF_BIT_10
#define PHY_MR17_RFAULT_IE DEF_BIT_09
#define PHY_MR17_ANEGCOMP_IE DEF_BIT_08
#define PHY_MR17_JABBER_INT DEF_BIT_07
#define PHY_MR17_RXER_INT DEF_BIT_06
#define PHY_MR17_PRX_INT DEF_BIT_05
#define PHY_MR17_PDF_INT DEF_BIT_04
#define PHY_MR17_LPACK_INT DEF_BIT_03
#define PHY_MR17_LSCHG_INT DEF_BIT_02
#define PHY_MR17_RFAULT_INT DEF_BIT_01
#define PHY_MR17_ANEGCOMP_INT DEF_BIT_00
#define PHY_MR18_ANEGF DEF_BIT_12
#define PHY_MR18_DPLX DEF_BIT_11
#define PHY_MR18_RATE DEF_BIT_10
#define PHY_MR18_RXSD DEF_BIT_09
#define PHY_MR18_RX_LOCK DEF_BIT_08
#define PHY_MR19_TXO 0xC000
#define PHY_MR23_LED1 0x00F0
#define PHY_MR23_LED0 0x000F
#define PHY_MR24_PD_MODE DEF_BIT_07
#define PHY_MR24_AUTO_SW DEF_BIT_06
#define PHY_MR24_MDIX DEF_BIT_05
#define PHY_MR24_MDIX_CM DEF_BIT_04
#define PHY_MR24_MDIX_SD 0x000F
/*
*********************************************************************************************************
*********************************************************************************************************
* GLOBAL FUNCTIONS
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* NetNIC_PhyInit()
*
* Description : Initiaze the PHY
*
* Argument(s) : none
*
* Return(s) : none
*
* Caller(s) : EMAC_Init().
*********************************************************************************************************
*/
void NetNIC_PhyInit (NET_ERR *perr)
{
volatile CPU_INT16U reg_val;
NetNIC_PhyRegWr(0, PHY_MR00, PHY_MR00_RESET, perr); /* Reset the PHY */
while ((NetNIC_PhyRegRd(0, PHY_MR00, perr) & PHY_MR00_RESET) != 0) {
;
}
NetNIC_PhyAutoNeg(); /* Do link auto-negotiation */
NetNIC_ConnStatus = NetNIC_PhyLinkState(); /* Set NetNIC_ConnStatus according to link state */
if (NetNIC_ConnStatus == DEF_ON) {
NetNIC_LinkUp();
} else {
NetNIC_LinkDown();
}
reg_val = NetNIC_PhyRegRd(0, PHY_MR17, perr); /* Clear interrupts */
NetNIC_PhyRegWr(0, PHY_MR17, 0, perr); /* Clear interrupt enables */
NetNIC_PhyRegWr(0, PHY_MR17, PHY_MR17_LSCHG_IE, perr); /* Enable link state change interrupt */
*perr = NET_PHY_ERR_NONE;
}
/*
*********************************************************************************************************
* NetNIC_PhyAutoNeg()
*
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