can.c

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

//! \e pClkParms->uSJW are in units of bit time quanta.
//! The actual quantum time is determined by the
//! \e pClkParms->uQuantumPrescaler value, which will be divided into the CAN
//! module clock.
//!
//! The total bit time, in quanta, will be the sum of the two Seg
//! parameters, as follows:
//!
//!     bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
//!
//!
//! Note that the Sync_Seg is always one quantum in duration, and will be
//! added to derive the correct duration of Prop_Seg and Phase1_Seg.
//!
//! The equation to determine the actual bit rate is as follows:
//!
//! CAN Clock /
//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1)/(\e uQuantumPrescaler))
//!
//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
//! \e uQuantumPrescaler = 1 and a 6MHz CAN clock, that the bit rate will be
//! (8Mhz)/((5 + 2 + 1)/1) or 1 MBit/sec.
//!
//! \return None.
//
//*****************************************************************************
void
CANSetBitTiming(unsigned long ulBase,
                tCANBitClkParms *pClkParms)
{
    unsigned int uBitReg;
    unsigned int uSavedInit;

    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    ASSERT(pClkParms != 0);
    ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
           (pClkParms->uSyncPropPhase1Seg <= 16));
    ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
    ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
    ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
           (pClkParms->uQuantumPrescaler >= 1));

    //
    // To set the bit timing register, the controller must be placed
    // in init mode (if not already), and also configuration change
    // bit enabled.  State of the init bit should be saved so it can
    // be restored at the end.
    //
    uSavedInit = CANReadReg(ulBase + CAN_O_CTL);
    CANWriteReg(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);

    //
    // Set the bit fields of the bit timing register according to the parms
    //
    uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2;
    uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1;
    uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW;
    uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP;
    CANWriteReg(ulBase + CAN_O_BIT, uBitReg);

    //
    // Set the divider upper bits in the extension register
    //
    CANWriteReg(ulBase + CAN_O_BRPE,
        ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE);
    //
    // Clear the config change bit, and restore the init bit
    //
    uSavedInit &= ~CAN_CTL_CCE;

    //
    // If Init was not set before, then clear it.
    //
    if(uSavedInit & CAN_CTL_INIT)
    {
        uSavedInit &= ~CAN_CTL_INIT;
    }
    CANWriteReg(ulBase + CAN_O_CTL, uSavedInit);
}

//*****************************************************************************
//
//! Get CAN controller interrupt number.
//!
//! \param ulBase base address of the selected CAN controller
//!
//! Given a CAN controller base address, returns the corresponding interrupt
//! number.
//!
//! \return Returns a CAN interrupt number, or -1 if \e ulPort is invalid.
//
//*****************************************************************************
long
CANGetIntNumber(unsigned long ulBase)
{
    long lIntNumber;

    //
    // Return the interrupt number for the given CAN controller.
    //
    switch(ulBase)
    {
        case CAN0_BASE:
        {
            lIntNumber = INT_CAN0;
            break;
        }
        case CAN1_BASE:
        {
            lIntNumber = INT_CAN1;
            break;
        }
        case CAN2_BASE:
        {
            lIntNumber = INT_CAN2;
            break;
        }
        default:
        {
            lIntNumber = -1;
        }
    }
    return(lIntNumber);
}

//*****************************************************************************
//
//! Registers an interrupt handler for the CAN controller.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled CAN interrupts occur.
//!
//! This function registers the interrupt handler in the interrupt vector
//! table, and enables CAN interrupts on the interrupt controller; specific
//! CAN interrupt sources must be enabled using CANIntEnable().  The
//! interrupt handler being registered must clear the source of the interrupt
//! using CANIntClear();
//!
//! If the application is using a static interrupt vector table stored
//! in flash, then it is not necessary to register the interrupt handler
//! this way.  Instead, IntEnable() should be used to enable CAN interrupts
//! on the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    unsigned long ulIntNumber;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));

    //
    // Get the actual interrupt number for this CAN controller.
    //
    ulIntNumber = CANGetIntNumber(ulBase);

    //
    // Register the interrupt handler.
    //
    IntRegister(ulIntNumber, pfnHandler);

    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(ulIntNumber);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for the CAN controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function unregisters the previously registered interrupt handler
//! and disables the interrupt on the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntUnregister(unsigned long ulBase)
{
    unsigned long ulIntNumber;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));

    //
    // Get the actual interrupt number for this CAN controller.
    //
    ulIntNumber = CANGetIntNumber(ulBase);

    //
    // Register the interrupt handler.
    //
    IntUnregister(ulIntNumber);

    //
    // Disable the CAN interrupt.
    //
    IntDisable(ulIntNumber);
}

//*****************************************************************************
//
//! Enables individual CAN controller interrupt sources.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param eIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables specific interrupt sources of the CAN controller.  Only enabled
//! sources will cause a processor interrupt.
//!
//! The parameter \e eIntFlags is the logical OR of any of the following:
//!
//! - CAN_INT_ERROR - controller error condition has occurred
//! - CAN_INT_STATUS - a message transfer completed, or bus error detected
//! - CAN_INT_MASTER - allow CAN controller to generate interrupts
//!
//! In order to generate any interrupts, CAN_INT_MASTER must be enabled.
//! Further, for any particular transaction from a message object to
//! generate an interrupt, that message object must have interrupts enabled
//! (see CANMessageSet()).  CAN_INT_ERROR will generate an interrupt if the
//! controller enters the "busoff" condition, or if the error counters reach a
//! limit.  CAN_INT_STATUS will generate an interrupt under quite a few status
//! conditions and may provide more interrupts than the application needs to
//! handle.  When an interrupt occurs, use CANIntStatus() to determine the
//! cause.
//!
//! \return None.
//
//*****************************************************************************
void
CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);

    //
    // Enable the specified interrupts.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) | ulIntFlags);
}

//*****************************************************************************
//
//! Disables individual CAN controller interrupt sources.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param eIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the specified CAN controller interrupt sources.  Only enabled
//! interrupt sources can cause a processor interrupt.
//!
//! The parameter \e eIntFlags has the same definition as in the function
//! CANIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    ASSERT((ulIntFlags & ~(CAN_CTL_EIE | CAN_CTL_SIE | CAN_CTL_IE)) == 0);

    //
    // Disable the specified interrupts.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) & ~(ulIntFlags));
}

//*****************************************************************************
//
//! Gets the current CAN controller interrupt status.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param eIntStsReg indicates which interrupt status register to read
//!
//! Returns the value of one of two interrupt status registers.  The
//! interrupt status register read is determined by the parameter
//! \e eIntStsReg, which can have one of the following values:
//! - CAN_INT_STS_CAUSE - indicates the cause of the interrupt
//! - CAN_INT_STS_OBJECT - indicates pending interrupts of all message objects
//!
//! CAN_INT_STS_CAUSE returns the value of the controller interrupt register
//! and indicates the cause of the interrupt.  It will be a value of
//! CAN_INT_INTID_STATUS if the cause is a status interrupt.  In this case,
//! the status register should be read with the CANStatusGet() function.
//! Calling this function to read the status will also clear the status
//! interrupt.  If the value of the interrupt register is in the range 1-32,
//! then this indicates the number of the highest priority message object that
//! has an interrupt pending. The message object interrupt can be cleared by
//! using the CANIntClear() function, or by reading the message using
//! CANMessageGet() in the case of a received message.  The interrupt handler
//! can read the interrupt status again to make sure all pending interrupts are
//! cleared before returning from the interrupt.
//!
//! CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
//! have pending interrupts.  This can be used to discover all of the
//! pending interrupts at once, as opposed to repeatedly reading the interrupt
//! register by using CAN_INT_STS_CAUSE.
//!
//! \return The value of one of the interrupt status registers.
//
//*****************************************************************************
unsigned long
CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
{
    unsigned long ulStatus;

    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));

    //
    // See which status the caller is looking for.
    //
    switch(eIntStsReg)
    {
        //
        // The caller wants the global interrupt status for the CAN controller
        // specified by ulBase.
        //
        case CAN_INT_STS_CAUSE:
        {
            ulStatus = CANReadReg(ulBase + CAN_O_INT);
            break;
        }
        //
        // The caller wants the current message status interrupt for all
        // messages.
        //
        case CAN_INT_STS_OBJECT:
        {
            //
            // Read and combine both 16 bit values into one 32bit status.
            //
            ulStatus = (CANReadReg(ulBase + CAN_O_MSGINT1) &
                        CAN_MSGINT1_INTPND);
            ulStatus |= (CANReadReg(ulBase + CAN_O_MSGINT2) << 16);
            break;
        }
        default:
        {
            ulStatus = 0;
            break;
        }
    }
    //
    // Return the interrupt status value
    //
    return(ulStatus);
}

//*****************************************************************************
//
//! This call is used to clears a CAN interrupt source.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param ulIntClr is a value indicating which interrupt source to clear
//!
//! This function can be used to clear a specific interrupt source.  The
//! parameter \e ulIntClr should be one of the following values:
//! - CAN_INT_INTID_STATUS - Clears a status interrupt.
//! - 1-32 - Clear the specified message object interrupt
//!
//! It is not necessary to use this function to clear an interrupt.  This
//! should only be used if the application wants to clear an interrupt source
//! without taking the normal interrupt action.
//!
//! Normally, the status interrupt is cleared by reading the controller status,
//! by calling CANStatusGet().  A specific message object interrupt is normally
//! cleared by reading the message object (see CANMessageGet()).
//!
//! \return None.
//
//*****************************************************************************
void
CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
{
    //
    // Check the arguments.
    //
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    ASSERT((ulIntClr == CAN_INT_INTID_STATUS) ||
           ((ulIntClr>=1) && (ulIntClr <=32)));

    if(ulIntClr == CAN_INT_INTID_STATUS)
    {
        //
        // Simply read and discard the status to clear the interrupt.
        //
        CANReadReg(ulBase + CAN_O_STS);
    }
    else
    {
        //
        // Wait to be sure that this interface is not busy.
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }

        //
        // Only change the interrupt pending state by setting only the
        // CAN_IFCMSK_CLRINTPND bit.
        //
        CANWriteReg(ulBase + CAN_O_IF1CMSK, CAN_IFCMSK_CLRINTPND);

        //
        // Send the clear pending interrupt command to the CAN controller.
        //
        CANWriteReg(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IFCRQ_MNUM_MSK);

        //
        // Wait to be sure that this interface is not busy.
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }
    }
}