can.c

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

//*****************************************************************************
//
// can.c - Driver for the CAN module.
//
// Copyright (c) 2006-2007 Luminary Micro, Inc.  All rights reserved.
// 
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 1234-conf of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "../hw_nvic.h"
#include "../hw_can.h"
#include "debug.h"
#include "interrupt.h"
#include "sysctl.h"
#include "can.h"

//*****************************************************************************
//
// This is the maximum number that can be stored as an 11bit Message
// identifier
//
//*****************************************************************************
#define CAN_MAX_11BIT_MSG_ID    (0x7ff)

//*****************************************************************************
//
// This is used as the loop delay for accessing the CAN controller registers.
//
//*****************************************************************************
#define CAN_RW_DELAY            (5)

//*****************************************************************************
//
//! Reads a CAN controller register.
//!
//! \param ulRegAddress This holds the full address of the CAN register to be
//!     set.
//!
//! This function takes care of the synchronization necessary to read from a
//! CAN controller register.
//!
//! \note This call takes care of delay necessary so care should be taken
//!     when accessing the registers directly.
//!
//! \return The current value of the register that was requested by
//!     ulRegAddress.
//*****************************************************************************
unsigned long
CANReadReg(unsigned long ulRegAddress)
{
    volatile int iDelay;
    unsigned long ulRetVal;
    unsigned long ulIntNumber;
    unsigned long ulReenableInts;

    ulIntNumber = CANGetIntNumber(ulRegAddress & 0xfffff000);

    ASSERT(ulIntNumber != (unsigned long)-1);

    //
    // Remember current state so that we only reenable CAN interrupts if they
    // were already enabled.
    //
    ulReenableInts = HWREG(NVIC_DIS1) & (1 << (ulIntNumber - 48));

    if(ulReenableInts)
    {
        IntDisable(ulIntNumber);
    }

    //
    // Trigger the inital read to the CAN controller.  The value returned at
    // this point is not valid.
    //
    HWREG(ulRegAddress);

    for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
    {
    }

    //
    // Do the final read that has the valid value of the register.
    //
    ulRetVal = HWREG(ulRegAddress);

    //
    // Reenable CAN interrupts if they were enabled before this call.
    //
    if(ulReenableInts)
    {
        IntEnable(ulIntNumber);
    }

    return(ulRetVal);
}

//*****************************************************************************
//
//! Writes a CAN controller register.
//!
//! \param ulRegAddress This holds the full address of the CAN register to be
//!     set.
//! \param ulRegValue This should be set to the value to write into the
//!     register specified by ulRegAddress.
//!
//! This function takes care of the synchronization necessary to write to a
//! CAN controller register.  The call overhead takes care of delay necessary
//! so care should be taken when accessing the registers directly.
//!
//! \note This call takes care of delay necessary so care should be taken
//!     when accessing the registers directly.
//!
//! \return None.
//*****************************************************************************
void
CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue)
{
    volatile int iDelay;

    //
    // Trigger the inital write to the CAN controller.  The value will not make
    // it out to the CAN controller for CAN_RW_DELAY cycles.
    //
    HWREG(ulRegAddress) = ulRegValue;

    for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
    {
    }
}

//*****************************************************************************
//
//! This function copies data from a buffer to the CAN Data registers.
//!
//! \param pucData
//!     This holds the pointer to the data to be written out to the CAN
//!     controller's data registers.
//! \param pulRegister
//!     This holds the unsigned long pointer to the first register of the CAN
//!     controller's data registers.  For example in order to use the IF1
//!     register set on CAN controller 0 the value would be: (CAN0_BASE
//!     + CAN_O_IF1DA1)
//! \param iSize
//!     This holds the number of bytes to copy into the CAN controller.
//!
//! This function takes the steps necessary to copy data from a contiguous
//! buffer in memory into the non-contiguous data registers used by the CAN
//! controller.
//!
//! \return None.
//*****************************************************************************
void
CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister,
             int iSize)
{
    int iIdx;
    unsigned long ulValue;

    //
    // Loop always copies 1 or 2 bytes per iteration.
    //
    for(iIdx = 0; iIdx < iSize; )
    {

        //
        // Write out the data 16 bits at a time since this is how the
        // registers are aligned in memory.
        //
        ulValue = pucData[iIdx++];

        //
        // Only write the second byte if needed otherwise it will be zero.
        //
        if(iIdx < iSize)
        {
            ulValue |= (pucData[iIdx++] << 8);
        }
        CANWriteReg((unsigned long)(pulRegister++), ulValue);
    }
}

//*****************************************************************************
//
//! This function copies data from a buffer to the CAN Data registers.
//!
//! \param pucData
//!     This holds the pointer to location to store the data read from the CAN
//!     controller's data registers.
//! \param pulRegister
//!     This holds the unsigned long pointer to the first register of the CAN
//!     controller's data registers.  For example in order to use the IF1
//!     register set on CAN controller 1 the value would be: (CAN0_BASE
//!     + CAN_O_IF1DA1)
//! \param iSize
//!     This holds the number of bytes to copy from the CAN controller.
//!
//! This function takes the steps necessary to copy data to a contiguous
//! buffer in memory from the non-contiguous data registers used by the CAN
//! controller.
//!
//! \return None.
//*****************************************************************************
void
CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister,
             int iSize)
{
    int iIdx;
    unsigned long ulValue;

    //
    // Loop always copies 1 or 2 bytes per iteration.
    //
    for(iIdx = 0; iIdx < iSize; )
    {

        //
        // Read out the data 16 bits at a time since this is how the
        // registers are aligned in memory.
        //
        ulValue = CANReadReg((unsigned long)(pulRegister++));

        pucData[iIdx++] = (unsigned char)ulValue;

        //
        // Only read the second byte if needed.
        //
        if(iIdx < iSize)
        {
            pucData[iIdx++] = (unsigned char)(ulValue >> 8);
        }
    }
}

//*****************************************************************************
//
//! Initializes the CAN controller after reset.
//!
//! \param ulBase is the base address of the CAN controller.
//!
//! After reset, the CAN controller is left in the disabled state.  However,
//! the memory used for message objects contains undefined values and must
//! be cleared prior to enabling the CAN controller the first time.
//! This prevents unwanted transmission or reception of data before the message
//! objects are configured.  This function must be called before enabling the
//! controller the first time.
//!
//! \return None.
//
//*****************************************************************************
void
CANInit(unsigned long ulBase)
{
    int iMsg;

    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    //
    // Place CAN controller in init state, regardless of previous state
    // This will put controller in idle, and allow the message object
    // RAM to be programmed.
    //
    CANWriteReg(ulBase + CAN_O_CTL, CAN_CTL_INIT);

    //
    // Wait for busy bit to clear
    //
    while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
    {
    }

    //
    // Clear the message value bit in the arbitration register.
    // This indicates the message is not valid and is a "safe"
    // condition to leave the message object.  The same arb reg
    // is used to program all the message objects.
    //
    CANWriteReg(ulBase + CAN_O_IF1CMSK, CAN_IFCMSK_WRNRD | CAN_IFCMSK_ARB |
        CAN_IFCMSK_CONTROL);
    CANWriteReg(ulBase + CAN_O_IF1ARB2, 0);
    CANWriteReg(ulBase + CAN_O_IF1MCTL, 0);

    //
    // Loop through to program all 32 message objects
    //
    for(iMsg = 1; iMsg <= 32; iMsg++)
    {
        //
        // Wait for busy bit to clear
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }

        //
        // Initiate programming the message object
        //
        CANWriteReg(ulBase + CAN_O_IF1CRQ, iMsg);
    }

    CANWriteReg(ulBase + CAN_O_IF1CMSK, CAN_IFCMSK_NEWDAT |
        CAN_IFCMSK_CLRINTPND);

    //
    // Loop through to program all 32 message objects
    //
    for(iMsg = 1; iMsg <= 32; iMsg++)
    {
        //
        // Wait for busy bit to clear
        //
        while(CANReadReg(ulBase + CAN_O_IF1CRQ) & CAN_IFCRQ_BUSY)
        {
        }

        //
        // Initiate programming the message object
        //
        CANWriteReg(ulBase + CAN_O_IF1CRQ, iMsg);
    }

    //
    // Acknowledge any pending status interrupts.
    //
    CANReadReg(ulBase + CAN_O_STS);
}

//*****************************************************************************
//
//! Enables the CAN controller.
//!
//! \param ulBase is the base address of the CAN controller.
//!
//! Enables the CAN controller for message processing.  Once enabled, the
//! controller will automatically transmit any pending frames, and process
//! any received frames.  The controller can be stopped by calling
//! CANDisable().  Prior to calling CANEnable(), CANInit() should have been
//! called to initialize the controller and the CAN bus clock should be
//! configured by calling CANSetBitTiming().
//!
//! \return None.
//
//*****************************************************************************
void
CANEnable(unsigned long ulBase)
{
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    //
    // Clear the init bit in the control register.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) & ~CAN_CTL_INIT);
}

//*****************************************************************************
//
//! Disables the CAN controller.
//!
//! \param ulBase is the base address of the CAN controller to disable.
//!
//! Disables the CAN controller for message processing.  When disabled, the
//! controller will no longer automatically process data on the CAN bus.
//! The controller can be restarted by calling CANEnable().  The state of the
//! CAN controller is left as it was before this call.
//!
//! \return None.
//
//*****************************************************************************
void
CANDisable(unsigned long ulBase)
{
    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    //
    // Set the init bit in the control register.
    //
    CANWriteReg(ulBase + CAN_O_CTL,
                CANReadReg(ulBase + CAN_O_CTL) | CAN_CTL_INIT);
}

//*****************************************************************************
//
//! Reads the current settings for the CAN controller bit timing.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pClkParms points to a structure to hold the parameters
//!
//! Read the current configuration of the CAN controller bit clock timing,
//! and stores the resulting information in the structure supplied by the
//! caller.  Refer to CANSetBitTiming() for the meaning of the information
//! that is returned in the structure pointed to by \e pClkParms.
//!
//! \return None.
//
//*****************************************************************************
void
CANGetBitTiming(unsigned long ulBase,
                tCANBitClkParms *pClkParms)
{
    unsigned int uBitReg;

    ASSERT((ulBase == CAN0_BASE) ||
           (ulBase == CAN1_BASE) ||
           (ulBase == CAN2_BASE));
    ASSERT(pClkParms != 0);

    //
    // Read out all the bit timing values from the CAN controller registers.
    //
    uBitReg = CANReadReg(ulBase + CAN_O_BIT);
    pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2) >> 12) + 1;
    pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1) >> 8) + 1;
    pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW) >> 6) + 1;
    pClkParms->uQuantumPrescaler = ((uBitReg & CAN_BIT_BRP) |
    ((CANReadReg(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE) << 6)) + 1;
}

//*****************************************************************************
//
//! Configures the CAN controller bit timing.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param pClkParms points to the structure with the clock parameters
//!
//! Configures the various timing parameters for the CAN bus bit timing:
//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
//! the Synchronization Jump Width.  The values for Propagation and Phase
//! Buffer 1 segments are derived from the combination parameter
//! \e pClkParms->uSyncPropPhase1Seg.  Phase Buffer 2 is determined from the
//! parameter \e pClkParms->uPhase2Seg.  These two parameters, along with