ethernet.c

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

//! packet is available in the TX FIFO.
//!
//! \return This function will return \b true if a space is available in the
//! TX FIFO, otherwise, will return \b false.
//
//*****************************************************************************
tBoolean
EthernetSpaceAvail(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Return Empty (TRUE) or Full (FALSE) status of the FIFO
    //
    return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) == 0);
}

//*****************************************************************************
//
//! Receives a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is the maximum data to be read into the buffer
//!
//! Gets a packet from the receive FIFO of the controller and places it into
//! the buffer.  If no packet is available, the function will return a
//! -1 immediately.  Otherwise, the function will process the next packet in
//! the RX FIFO and return a the number of bytes read
//!
//! \note This function will return immediately if no packet is available.
//!
//! \return
//!     -1  - No packet available
//!     -2  - Error in receive packet
//!     -n  - Packet too large for buffer, truncated
//!     +n  - Number of bytes in the Rx Packet
//
//*****************************************************************************
long
EthernetPacketNonBlockingGet(unsigned long ulBase, unsigned char *pucBuf,
                             long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Check to see if any packets are available
    //
    if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR) == 0)
    {
        return(-1);
    }

    //
    // Read the packet, and return
    //
    return(EthernetInternalGetPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Waits for a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is the maximum data to be read into the buffer
//!
//! Gets a packet from the receive FIFO of the controller and places it into
//! the buffer.  If no packet is available, the function will will wait until
//! one arrives in the RX FIFO of the Controller before processing it and
//! returning.
//!
//! \note This function is blocking, and will not return until a packet
//! arrives.
//!
//! \return
//!     -2  - Error in receive packet
//!     -n  - Packet too large for buffer, truncated
//!     +n  - Number of bytes in the Rx Packet
//
//*****************************************************************************
long
EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
                  long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Wait for a packet to become available
    //
    while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR) == 0)
    {
    }

    //
    // Read the packet
    //
    return(EthernetInternalGetPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Sends a packet to the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is length of the packet to be transmitted.
//!
//! Writes the packet contained in \e pucBuf into the transmit FIFO of the
//! controller, and then activates the transmitter for this packet.  If no
//! space is available in the TX FIFO, the function will return a \b false
//! code immediately.  If space is available, the function will return once
//! the packet has been placed into the TX FIFO, and will not wait for the
//! packet transmissionto be completed.
//!
//! \note This function does not block, and will return immediately if no
//! space is available for the transmit packet.
//!
//! \sa Refer to \e ethernet.h for more details about the format of the packet
//! structure, \e tEthernetPacket.
//!
//! \return
//!     -1  - No space available in transmit fifo
//!     -2  - Error in transmission of packet
//!     -n  - Packet too large for transmit fifo, not sent
//!     +n  - Number of bytes transmitted
//
//*****************************************************************************
long
EthernetPacketNonBlockingPut(unsigned long ulBase, unsigned char *pucBuf,
                             long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Check if TX Packet in progress and return false
    //
    if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
    {
        return(-1);
    }

    //
    // Send the packet and return
    //
    return(EthernetInternalPutPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Waits to send a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is length of the packet to be transmitted.
//!
//!
//! Writes the packet contained in \e pucBuf into the transmit FIFO of the
//! controller, and then activates the transmitter for this packet.  If a 
//! packet is currently in progress, this function will wait till the current
//! packet is completed, and will then write the new packet into the FIFO and
//! activate the transmitter.  The function will return once the packet has
//! been placed into the TX FIFO, and will not wait for the packet transmission
//! to be completed.
//!
//! \note This function blocks, and will wait until space is available for the
//! transmit packet before returning.
//!
//! \return
//!     -2  - Error in transmission of packet
//!     -n  - Packet too large for transmit fifo, not sent
//!     +n  - Number of bytes transmitted
//
//*****************************************************************************
long
EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
                  long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Wait for current packet (if any) to complete
    //
    while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
    {
    }

    //
    // Send the packet and return
    //
    return(EthernetInternalPutPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Registers an interrupt handler for an Ethernet interrupt.
//!
//! \param ulBase is the base address of the controller.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled Ethernet interrupts occur.
//!
//! This function does the actual registering of the interrupt handler.  This
//! will enable the global interrupt in the interrupt controller; specific
//! Ethernet interrupts must be enabled via EthernetIntEnable().  It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pfnHandler != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_ETH, pfnHandler);

    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(INT_ETH);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for an Ethernet interrupt.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function does the actual unregistering of the interrupt handler.  It
//! will clear the handler to be called when an Ethernet interrupt occurs.
//! This will also mask off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntUnregister(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Disable the interrupt.
    //
    IntDisable(INT_ETH);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_ETH);
}

//*****************************************************************************
//
//! Enables individual Ethernet interrupt sources.
//!
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated Ethernet interrupt sources.  Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The parameter \e ulIntFlags is the logical OR of any of the following:
//!
//! - ETH_INT_PHY - An interrupt from the PHY has occured.  The PHY_MR17
//!     register must be read to determine the PHY interrupt that has
//!     occurred.
//! - ETH_INT_MDIO - This interrupt indicates that a transaction on the
//!     management interface has completed sucessfully.
//! - ETH_INT_RXER - This interrupt indicates that an error has occurred
//!     during reception of a frame.  This error can indicated a length
//!     mismatch, a CRC failure, or an error indication from the PHY.
//! - ETH_INT_RXOF - This interrupt indicates that a frame has been received
//!     that exceeds the available space in the RX FIFO.
//! - ETH_INT_TX - This interrupt indicates that the packet stored in the TX
//!     FIFO has been successfully transmitted.
//! - ETH_INT_TXER - This interrupt indicates that an error has occurred
//!     during the transmission of a packet.  This error can be either a
//!     retry failure during the backoff process, or an invalid length stored
//!     in the TX FIFO.
//! - ETH_INT_RX - This interrupt indicates that one (or more) packets are
//!     available in the RX FIFO for processing.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
                ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));

    //
    // Enable the specified interrupts.
    //
    HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
}

//*****************************************************************************
//
//! Disables individual Ethernet interrupt sources.
//!
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated Ethernet interrupt sources.  Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The parameter \e ulIntFlags has the same definition as the same parameter
//! to EthernetIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
                ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));

    //
    // Disable the specified interrupts.
    //
    HWREG(ulBase + MAC_O_IM) &= ~(ulIntFlags);
}

//*****************************************************************************
//
//! Gets the current Ethernet interrupt status.
//!
//! \param ulBase is the base address of the controller.
//! \param bMasked is false if the raw interrupt status is required and true
//! if the masked interrupt status is required.
//!
//! This returns the interrupt status for the Ethernet Controller.  Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! values described in EthernetIntEnable().
//
//*****************************************************************************
unsigned long
EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
{
    unsigned long ulStatus;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Read the unmasked status
    //
    ulStatus = HWREG(ulBase + MAC_O_IS);

    //