ethernet.c

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

//*****************************************************************************
//
// ethernet.c - Driver for the Integrated Ethernet Controller
//
// Copyright (c) 2006-2007 Luminary Micro, Inc.  All rights reserved.
// 
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 1234-conf of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup ethernet_api
//! @{
//
//*****************************************************************************

#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "../hw_ethernet.h"
#include "debug.h"
#include "interrupt.h"
#include "sysctl.h"
#include "ethernet.h"

//*****************************************************************************
//
// Internal function declarations and macros for Ethernet driver
//
//*****************************************************************************
static long EthernetInternalGetPacket(unsigned long ulBase,
                                      unsigned char *pucBuf,
                                      long lBufLen);
static long EthernetInternalPutPacket(unsigned long ulBase,
                                      unsigned char *pucBuf,
                                      long lBufLen);

//*****************************************************************************
//
//! Initializes the Ethernet Controller for operation
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will prepare the Ethernet Controller for first time use in
//! a given hardware/software configuration.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetInit(unsigned long ulBase)
{
    unsigned long ulDiv;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Set the Management Clock Divider register for access to the PHY
    // register set (via EthernetPHYRead/Write)
    //
    // The MDC clock divided down from the system clock using the following
    // formula.  A maximum of 2.5MHz is allowed for F(mdc).
    //
    //      F(mdc) = F(sys) / (2 * (div + 1))
    //      div = (F(sys) / (2 * F(mdc))) - 1
    //      div = (F(sys) / 2 / F(mdc)) - 1
    //
    // Note: Because we should round up, to ensure we don't violate the
    // maximum clock speed, we can simplify this as follows:
    //
    //      div = F(sys) / 2 / F(mdc)
    //
    // For example, given a system clock of 6.0MHz, and an div value of 1,
    // the mdc clock would be programmed as 1.5 MHz.
    //
    ulDiv = (SysCtlClockGet() / 2) / 2500000;
    HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV);
}

//*****************************************************************************
//
//! Sets the configuration of the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param ulConfig is the configuration for the controller.
//!
//! This function will configure the transmit and receive parameters
//! of the controller.  The \e ulConfig parameter is the logical OR of the
//! following values.
//!
//! - ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer inputs
//! - ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
//! - ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
//! - ETH_CFG_RX_AMULEN - Enable reception of multicast packets
//! - ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
//! - ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
//! - ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
//!
//! \return None.
//
//*****************************************************************************
void
EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
{
    unsigned long ulTemp;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
                    ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
                    ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
                    ETH_CFG_TS_TSEN)) == 0);

    //
    // Set the TX Configuration Register
    //
    ulTemp  = HWREG(ulBase + MAC_O_TCTL);
    ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
    ulTemp |= (ulConfig & 0x0FF);
    HWREG(ulBase + MAC_O_TCTL) = ulTemp;

    //
    // Set the RX Configuration Register
    //
    ulTemp  = HWREG(ulBase + MAC_O_RCTL);
    ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
    ulTemp |= ((ulConfig >> 8) & 0x0FF);
    HWREG(ulBase + MAC_O_RCTL) = ulTemp;

    //
    // Set the TS Configuration Register
    //
    ulTemp = HWREG(ulBase + MAC_O_TS);
    ulTemp &= ~(MAC_TS_TSEN);
    ulTemp |= ((ulConfig >> 16) & 0x0FF);
    HWREG(ulBase + MAC_O_TS) = ulTemp;
}

//*****************************************************************************
//
//! Gets the current configuration of the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will query the transmit and receive control registers of
//! the Ethernet Controller, and return those parameters in a bit-mapped
//! return code.
//!
//! \sa See the description for the EthernetConfigSet() function for more
//! details of the bit-mapped values.
//!
//! \return The bit-mapped configuration of transmit and receive parameters.
//
//*****************************************************************************
unsigned long
EthernetConfigGet(unsigned long ulBase)
{
    unsigned long ulConfig;
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Read and return TX/RX configuration, with ENABLE bits masked out, and
    // properly shifted to match the driver API macros.
    //
    ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
    ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~MAC_RCTL_RXEN) << 8;
    ulConfig |= (HWREG(ulBase + MAC_O_TCTL) & ~MAC_TCTL_TXEN);
    return(ulConfig);
}

//*****************************************************************************
//
//! Sets the MAC Address of the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the array of MAC-48 Address Octets
//!
//! This function will program the IEEE defined MAC-48 address into the
//! Ethernet Controller.  This address is used by the Ethernet Controller for
//! hardware level filtering of incoming Ethernet packets.
//!
//! The MAC-48 address is defined as 6 octets, illustrated by the fictitious
//! address below.  The numbers are presented in hexadecimal format.
//!
//!         AC-DE-48-00-00-80
//!
//! In this representation, the first three octets (AC-DE-48) are the
//! Organizationally Unique Identifier (OUI).  This is a number assigned by
//! the IEEE to an organization that requests a block of MAC addresses.  The
//! last three octets are a 24-bit number managed by the OUI owner to uniquely
//! identify a piece of hardware within that organization that is to be
//! connected to the Ethernet.
//!
//! In this representation, the octets are transmitted from left to right,
//! with the "AC" octet being transmitted first and the "80" octet being
//! transmitted last.  Within an octet, the bits are transmitted LSB to MSB.
//! For this address, the first bit to be transmitted would be "0", the LSB of
//! "AC", and the last bit to be transmitted would be "1", the MSB of "80".
//
//*****************************************************************************
void
EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
{
    unsigned long ulTemp;
    unsigned char *pucTemp = (unsigned char *)&ulTemp;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucMACAddr != 0);

    //
    // Program the MAC Address into the device
    //
    pucTemp[0] = pucMACAddr[0];
    pucTemp[1] = pucMACAddr[1];
    pucTemp[2] = pucMACAddr[2];
    pucTemp[3] = pucMACAddr[3];
    HWREG(ulBase + MAC_O_IA0) = ulTemp;
    ulTemp = 0;
    pucTemp[0] = pucMACAddr[4];
    pucTemp[1] = pucMACAddr[5];
    HWREG(ulBase + MAC_O_IA1) = ulTemp;
}

//*****************************************************************************
//
//! Gets the MAC Address of the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the location in which to store the
//! array of MAC-48 Address Octets
//!
//! \sa Refer to \e EthernetMACSet API description for more details about
//! the MAC address format.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
{
    unsigned long ulTemp;
    unsigned char *pucTemp = (unsigned char *)&ulTemp;
    
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucMACAddr != 0);

    //
    // Read the MAC Address from the device
    //
    ulTemp = HWREG(ulBase + MAC_O_IA0);
    pucMACAddr[0] = pucTemp[0];
    pucMACAddr[1] = pucTemp[1];
    pucMACAddr[2] = pucTemp[2];
    pucMACAddr[3] = pucTemp[3];
    ulTemp = HWREG(ulBase + MAC_O_IA1);
    pucMACAddr[4] = pucTemp[0];
    pucMACAddr[5] = pucTemp[1];
}

//*****************************************************************************
//
//! Enables the Ethernet Controller for normal operation.
//!
//! \param ulBase is the base address of the controller.
//!
//! Resets the receive FIFO, and enables the transmitter and receiver.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetEnable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Reset the RX FIFO
    //
    HWREG(ulBase + MAC_O_RCTL) |= (MAC_RCTL_RSTFIFO);

    //
    // Enable RXEN
    //
    HWREG(ulBase + MAC_O_RCTL) |= (MAC_RCTL_RXEN);

    //
    // Enable TXEN
    //
    HWREG(ulBase + MAC_O_TCTL) |= (MAC_TCTL_TXEN);

    //
    // Reset the RX FIFO, again
    //
    HWREG(ulBase + MAC_O_RCTL) |= (MAC_RCTL_RSTFIFO);

}

//*****************************************************************************
//
//! Disables the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! Waits for current transmit packet (if any) to complete, and disables
//! the transmitter and receiver.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetDisable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Reset the RX FIFO
    //
    HWREG(ulBase + MAC_O_RCTL) |= (MAC_RCTL_RSTFIFO);

    //
    // Disable TXEN
    //
    HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);

    //
    // Disable RXEN
    //
    HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);

    //
    // Reset the RX FIFO, again
    //
    HWREG(ulBase + MAC_O_RCTL) |= (MAC_RCTL_RSTFIFO);
}

//*****************************************************************************
//
//! Check for packet available from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will return the count of packets available in the RX FIFO.
//! If a packet is being read, this count will still include the current
//! packet, until the last WORD of the packet has been read from the FIFO.
//!
//! \return This function will return the number of packets in the RX FIFO.
//
//*****************************************************************************
long
EthernetPacketAvail(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Return number of packets available in the RX FIFO
    //
    return(HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR);
}

//*****************************************************************************
//
//! Check for packet space available in the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will query the controller and determine if space for a