hw_nvic.h

从Luminary官方网站下载的LM3S6000系列的UCos+Tcp/IP的源码, 经本人稍微修改后可直接在IAR6.2下编译通过,里面包括了LM3S6000系列的所有外设UART, PWn....

#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation

//*****************************************************************************
//
// The following define the bit fields in the NVIC_HFAULT_STAT register.
//
//*****************************************************************************
#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault

//*****************************************************************************
//
// The following define the bit fields in the NVIC_DEBUG_STAT register.
//
//*****************************************************************************
#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MM_ADDR register.
//
//*****************************************************************************
#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
#define NVIC_MM_ADDR_S          0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_FAULT_ADDR register.
//
//*****************************************************************************
#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
#define NVIC_FAULT_ADDR_S       0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_STACK register.
//
//*****************************************************************************
#define NVIC_EXC_STACK_DEEP     0x00000001  // Exception stack

//*****************************************************************************
//
// The following define the bit fields in the NVIC_EXC_NUM register.
//
//*****************************************************************************
#define NVIC_EXC_NUM_M          0x000003FF  // Exception number
#define NVIC_EXC_NUM_S          0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_COPRO register.
//
//*****************************************************************************
#define NVIC_COPRO_15_M         0xC0000000  // Coprocessor 15 access mask
#define NVIC_COPRO_15_DENIED    0x00000000  // Coprocessor 15 access denied
#define NVIC_COPRO_15_PRIV      0x40000000  // Coprocessor 15 privileged addess
#define NVIC_COPRO_15_FULL      0xC0000000  // Coprocessor 15 full access
#define NVIC_COPRO_14_M         0x30000000  // Coprocessor 14 access mask
#define NVIC_COPRO_14_DENIED    0x00000000  // Coprocessor 14 access denied
#define NVIC_COPRO_14_PRIV      0x10000000  // Coprocessor 14 privileged addess
#define NVIC_COPRO_14_FULL      0x30000000  // Coprocessor 14 full access
#define NVIC_COPRO_13_M         0x0C000000  // Coprocessor 13 access mask
#define NVIC_COPRO_13_DENIED    0x00000000  // Coprocessor 13 access denied
#define NVIC_COPRO_13_PRIV      0x04000000  // Coprocessor 13 privileged addess
#define NVIC_COPRO_13_FULL      0x0C000000  // Coprocessor 13 full access
#define NVIC_COPRO_12_M         0x03000000  // Coprocessor 12 access mask
#define NVIC_COPRO_12_DENIED    0x00000000  // Coprocessor 12 access denied
#define NVIC_COPRO_12_PRIV      0x01000000  // Coprocessor 12 privileged addess
#define NVIC_COPRO_12_FULL      0x03000000  // Coprocessor 12 full access
#define NVIC_COPRO_11_M         0x00C00000  // Coprocessor 11 access mask
#define NVIC_COPRO_11_DENIED    0x00000000  // Coprocessor 11 access denied
#define NVIC_COPRO_11_PRIV      0x00400000  // Coprocessor 11 privileged addess
#define NVIC_COPRO_11_FULL      0x00C00000  // Coprocessor 11 full access
#define NVIC_COPRO_10_M         0x00300000  // Coprocessor 10 access mask
#define NVIC_COPRO_10_DENIED    0x00000000  // Coprocessor 10 access denied
#define NVIC_COPRO_10_PRIV      0x00100000  // Coprocessor 10 privileged addess
#define NVIC_COPRO_10_FULL      0x00300000  // Coprocessor 10 full access
#define NVIC_COPRO_9_M          0x000C0000  // Coprocessor 9 access mask
#define NVIC_COPRO_9_DENIED     0x00000000  // Coprocessor 9 access denied
#define NVIC_COPRO_9_PRIV       0x00040000  // Coprocessor 9 privileged addess
#define NVIC_COPRO_9_FULL       0x000C0000  // Coprocessor 9 full access
#define NVIC_COPRO_8_M          0x00030000  // Coprocessor 8 access mask
#define NVIC_COPRO_8_DENIED     0x00000000  // Coprocessor 8 access denied
#define NVIC_COPRO_8_PRIV       0x00010000  // Coprocessor 8 privileged addess
#define NVIC_COPRO_8_FULL       0x00030000  // Coprocessor 8 full access
#define NVIC_COPRO_7_M          0x0000C000  // Coprocessor 7 access mask
#define NVIC_COPRO_7_DENIED     0x00000000  // Coprocessor 7 access denied
#define NVIC_COPRO_7_PRIV       0x00004000  // Coprocessor 7 privileged addess
#define NVIC_COPRO_7_FULL       0x0000C000  // Coprocessor 7 full access
#define NVIC_COPRO_6_M          0x00003000  // Coprocessor 6 access mask
#define NVIC_COPRO_6_DENIED     0x00000000  // Coprocessor 6 access denied
#define NVIC_COPRO_6_PRIV       0x00001000  // Coprocessor 6 privileged addess
#define NVIC_COPRO_6_FULL       0x00003000  // Coprocessor 6 full access
#define NVIC_COPRO_5_M          0x00000C00  // Coprocessor 5 access mask
#define NVIC_COPRO_5_DENIED     0x00000000  // Coprocessor 5 access denied
#define NVIC_COPRO_5_PRIV       0x00000400  // Coprocessor 5 privileged addess
#define NVIC_COPRO_5_FULL       0x00000C00  // Coprocessor 5 full access
#define NVIC_COPRO_4_M          0x00000300  // Coprocessor 4 access mask
#define NVIC_COPRO_4_DENIED     0x00000000  // Coprocessor 4 access denied
#define NVIC_COPRO_4_PRIV       0x00000100  // Coprocessor 4 privileged addess
#define NVIC_COPRO_4_FULL       0x00000300  // Coprocessor 4 full access
#define NVIC_COPRO_3_M          0x000000C0  // Coprocessor 3 access mask
#define NVIC_COPRO_3_DENIED     0x00000000  // Coprocessor 3 access denied
#define NVIC_COPRO_3_PRIV       0x00000040  // Coprocessor 3 privileged addess
#define NVIC_COPRO_3_FULL       0x000000C0  // Coprocessor 3 full access
#define NVIC_COPRO_2_M          0x00000030  // Coprocessor 2 access mask
#define NVIC_COPRO_2_DENIED     0x00000000  // Coprocessor 2 access denied
#define NVIC_COPRO_2_PRIV       0x00000010  // Coprocessor 2 privileged addess
#define NVIC_COPRO_2_FULL       0x00000030  // Coprocessor 2 full access
#define NVIC_COPRO_1_M          0x0000000C  // Coprocessor 1 access mask
#define NVIC_COPRO_1_DENIED     0x00000000  // Coprocessor 1 access denied
#define NVIC_COPRO_1_PRIV       0x00000004  // Coprocessor 1 privileged addess
#define NVIC_COPRO_1_FULL       0x0000000C  // Coprocessor 1 full access
#define NVIC_COPRO_0_M          0x00000003  // Coprocessor 0 access mask
#define NVIC_COPRO_0_DENIED     0x00000000  // Coprocessor 0 access denied
#define NVIC_COPRO_0_PRIV       0x00000001  // Coprocessor 0 privileged addess
#define NVIC_COPRO_0_FULL       0x00000003  // Coprocessor 0 full access

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_TYPE register.
//
//*****************************************************************************
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
#define NVIC_MPU_TYPE_IREGION_S 16
#define NVIC_MPU_TYPE_DREGION_S 8

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_CTRL register.
//
//*****************************************************************************
#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_NUMBER register.
//
//*****************************************************************************
#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
#define NVIC_MPU_NUMBER_S       0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_BASE register.
//
//*****************************************************************************
#define NVIC_MPU_BASE_ADDR_M    0xFFFFFF00  // Base address
#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
#define NVIC_MPU_BASE_ADDR_S    8
#define NVIC_MPU_BASE_REGION_S  0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_MPU_ATTR register.
//
//*****************************************************************************
#define NVIC_MPU_ATTR_ATTRS     0xFFFF0000  // Attributes
#define NVIC_MPU_ATTR_SRD       0x0000FF00  // Sub-region disable
#define NVIC_MPU_ATTR_SZENABLE  0x000000FF  // Region size

//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_CTRL register.
//
//*****************************************************************************
#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
#define NVIC_DBG_CTRL_MON_PEND  0x00008000  // Pend the monitor
#define NVIC_DBG_CTRL_MON_REQ   0x00004000  // Monitor request
#define NVIC_DBG_CTRL_MON_EN    0x00002000  // Debug monitor enable
#define NVIC_DBG_CTRL_MONSTEP   0x00001000  // Monitor step the core
#define NVIC_DBG_CTRL_S_SLEEP   0x00000400  // Core is sleeping
#define NVIC_DBG_CTRL_S_HALT    0x00000200  // Core status on halt
#define NVIC_DBG_CTRL_S_REGRDY  0x00000100  // Register read/write available
#define NVIC_DBG_CTRL_S_LOCKUP  0x00000080  // Core is locked up
#define NVIC_DBG_CTRL_C_RESET   0x00000010  // Reset the core
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug

//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_XFER register.
//
//*****************************************************************************
#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask

//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_DATA register.
//
//*****************************************************************************
#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
#define NVIC_DBG_DATA_S         0

//*****************************************************************************
//
// The following define the bit fields in the NVIC_DBG_INT register.
//
//*****************************************************************************
#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch

//*****************************************************************************
//
// The following define the bit fields in the NVIC_SW_TRIG register.
//
//*****************************************************************************
#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
#define NVIC_SW_TRIG_INTID_S    0

#endif // __HW_NVIC_H__