📄 omap2-audio-twl4030.h
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#define APLL_CTL_FREQ_19_2MHZ (0x5)#define APLL_CTL_FREQ_26_0MHZ (0x6)#define APLL_CTL_FREQ_38_4MHZ (0xF)#define BIT_APLL_CTL_APLL_INFREQ (0x000)#define BIT_APLL_CTL_APLL_INFREQ_M (0x0000000F)#define BIT_APLL_CTL_APLL_EN (0x004)#define BIT_APLL_CTL_APLL_EN_M (0x00000010)/* DTMF_CTL Fields */#define BIT_DTMF_CTL_TONE_EN (0x000)#define BIT_DTMF_CTL_TONE_EN_M (0x00000001)#define BIT_DTMF_CTL_DUAL_TONE_EN (0x001)#define BIT_DTMF_CTL_DUAL_TONE_EN_M (0x00000002)#define BIT_DTMF_CTL_TONE_PATTERN (0x002)#define BIT_DTMF_CTL_TONE_PATTERN_M (0x00000004)#define BIT_DTMF_CTL_TONE_MODE (0x003)#define BIT_DTMF_CTL_TONE_MODE_M (0x00000008)/* DTMF_PGA_CTL2 Fields */#define BIT_DTMF_PGA_CTL2_TONE3_GAIN (0x000)#define BIT_DTMF_PGA_CTL2_TONE3_GAIN_M (0x00000007)#define BIT_DTMF_PGA_CTL2_TONE4_GAIN (0x004)#define BIT_DTMF_PGA_CTL2_TONE4_GAIN_M (0x00000070)#define BIT_DTMF_PGA_CTL2_TONE_18DB_ATT (0x007)#define BIT_DTMF_PGA_CTL2_TONE_18DB_ATT_M (0x00000080)/* DTMF_PGA_CTL1 Fields */#define BIT_DTMF_PGA_CTL1_TONE1_GAIN (0x000)#define BIT_DTMF_PGA_CTL1_TONE1_GAIN_M (0x0000000F)#define BIT_DTMF_PGA_CTL1_TONE2_GAIN (0x004)#define BIT_DTMF_PGA_CTL1_TONE2_GAIN_M (0x000000F0)/* MISC_SET_1 Fields */#define BIT_MISC_SET_1_DIGMIC_LR_SWAP_EN (0x000)#define BIT_MISC_SET_1_DIGMIC_LR_SWAP_EN_M (0x00000001)#define BIT_MISC_SET_1_SPARE1 (0x001)#define BIT_MISC_SET_1_SPARE1_M (0x00000002)#define BIT_MISC_SET_1_SPARE2 (0x002)#define BIT_MISC_SET_1_SPARE2_M (0x00000004)#define BIT_MISC_SET_1_FMLOOP_EN (0x005)#define BIT_MISC_SET_1_FMLOOP_EN_M (0x00000020)#define BIT_MISC_SET_1_SCRAMBLE_EN (0x006)#define BIT_MISC_SET_1_SCRAMBLE_EN_M (0x00000040)#define BIT_MISC_SET_1_CLK64_EN (0x007)#define BIT_MISC_SET_1_CLK64_EN_M (0x00000080)/* PCMBTMUX Fields */#define BIT_PCMBTMUX_TNRXACT_BT (0x000)#define BIT_PCMBTMUX_TNRXACT_BT_M (0x00000001)#define BIT_PCMBTMUX_TNTXACT_BT (0x001)#define BIT_PCMBTMUX_TNTXACT_BT_M (0x00000002)#define BIT_PCMBTMUX_TNRXACT_PCM (0x002)#define BIT_PCMBTMUX_TNRXACT_PCM_M (0x00000004)#define BIT_PCMBTMUX_TNTXACT_PCM (0x003)#define BIT_PCMBTMUX_TNTXACT_PCM_M (0x00000008)#define BIT_PCMBTMUX_MUXRX_BT (0x005)#define BIT_PCMBTMUX_MUXRX_BT_M (0x00000020)#define BIT_PCMBTMUX_MUXRX_PCM (0x006)#define BIT_PCMBTMUX_MUXRX_PCM_M (0x00000040)#define BIT_PCMBTMUX_MUXTX_PCM (0x007)#define BIT_PCMBTMUX_MUXTX_PCM_M (0x00000080)/* RX_PATH_SEL Fields */#define BIT_RX_PATH_SEL_RXR1_SEL (0x000)#define BIT_RX_PATH_SEL_RXR1_SEL_M (0x00000003)#define BIT_RX_PATH_SEL_RXL1_SEL (0x002)#define BIT_RX_PATH_SEL_RXL1_SEL_M (0x0000000C)#define BIT_RX_PATH_SEL_RXR2_SEL (0x004)#define BIT_RX_PATH_SEL_RXR2_SEL_M (0x00000010)#define BIT_RX_PATH_SEL_RXL2_SEL (0x005)#define BIT_RX_PATH_SEL_RXL2_SEL_M (0x00000020)/* VDL_APGA_CTL Fields */#define BIT_VDL_APGA_CTL_VDL_PDZ (0x000)#define BIT_VDL_APGA_CTL_VDL_PDZ_M (0x00000001)#define BIT_VDL_APGA_CTL_VDL_DA_EN (0x001)#define BIT_VDL_APGA_CTL_VDL_DA_EN_M (0x00000002)#define BIT_VDL_APGA_CTL_VDL_FM_EN (0x002)#define BIT_VDL_APGA_CTL_VDL_FM_EN_M (0x00000004)#define BIT_VDL_APGA_CTL_VDL_GAIN_SET (0x003)#define BIT_VDL_APGA_CTL_VDL_GAIN_SET_M (0x000000F8)/* VIBRA_CTL Fields */#define BIT_VIBRA_CTL_VIVRA_EN (0x000)#define BIT_VIBRA_CTL_VIVRA_EN_M (0x00000001)#define BIT_VIBRA_CTL_VIBRA_DIR (0x001)#define BIT_VIBRA_CTL_VIBRA_DIR_M (0x00000002)#define BIT_VIBRA_CTL_VIBRA_AUDIO_SEL (0x002)#define BIT_VIBRA_CTL_VIBRA_AUDIO_SEL_M (0x0000000C)#define BIT_VIBRA_CTL_VIBRA_SEL (0x004)#define BIT_VIBRA_CTL_VIBRA_SEL_M (0x00000010)#define BIT_VIBRA_CTL_VIBRA_DIR_SEL (0x005)#define BIT_VIBRA_CTL_VIBRA_DIR_SEL_M (0x00000020)#define BIT_VIBRA_CTL_SPARE (0x006)#define BIT_VIBRA_CTL_SPARE_M (0x00000040)/* VIBRA_SET Fields */#define BIT_VIBRA_SET_VIBRA_AVG_VAL (0x000)#define BIT_VIBRA_SET_VIBRA_AVG_VAL_M (0x000000FF)/* VIBRA_PWM_SET Fields */#define BIT_VIBRA_PWM_SET_PWM_ON (0x000)#define BIT_VIBRA_PWM_SET_PWM_ON_M (0x000000FF)#define MICAM_GAIN_MIN (0x0)#define MICAM_GAIN_MAX (0x5)/* ANAMIC_GAIN Fields */#define BIT_ANAMIC_GAIN_MICAMPL_GAIN (0x000)#define BIT_ANAMIC_GAIN_MICAMPL_GAIN_M (0x00000007)#define BIT_ANAMIC_GAIN_MICAMPR_GAIN (0x003)#define BIT_ANAMIC_GAIN_MICAMPR_GAIN_M (0x00000038)/* MISC_SET_2 Fields */#define BIT_MISC_SET_2_SPARE1 (0x000)#define BIT_MISC_SET_2_SPARE1_M (0x00000001)#define BIT_MISC_SET_2_VRX_HPF_BYP (0x001)#define BIT_MISC_SET_2_VRX_HPF_BYP_M (0x00000002)#define BIT_MISC_SET_2_VTX_HPF_BYP (0x002)#define BIT_MISC_SET_2_VTX_HPF_BYP_M (0x00000004)#define BIT_MISC_SET_2_ARX_HPF_BYP (0x003)#define BIT_MISC_SET_2_ARX_HPF_BYP_M (0x00000008)#define BIT_MISC_SET_2_VRX_3RD_HPF_BYP (0x004)#define BIT_MISC_SET_2_VRX_3RD_HPF_BYP_M (0x00000010)#define BIT_MISC_SET_2_ATX_HPF_BYP (0x005)#define BIT_MISC_SET_2_ATX_HPF_BYP_M (0x00000020)#define BIT_MISC_SET_2_VTX_3RD_HPF_BYP (0x006)#define BIT_MISC_SET_2_VTX_3RD_HPF_BYP_M (0x00000040)#define BIT_MISC_SET_2_SPARE2 (0x007)#define BIT_MISC_SET_2_SPARE2_M (0x00000080)/************** INTERNAL DETAILS ********************//* * Mapping of OSS devices to TWL devices * TWL Device OSS MASK * ============================================================== * OUTPUT: * ======= * OUTPUT_STEREO_HEADSET SOUND_MASK_LINE1 * OUTPUT_HANDS_FREE_CLASSD SOUND_MASK_SPEAKER * OUTPUT_MONO_EARPIECE SOUND_MASK_PHONEOUT (mono Sink) * * INPUT: * ====== * INPUT_HEADSET_MIC SOUND_MASK_LINE * INPUT_MAIN_MIC + INPUT_SUB_MIC SOUND_MASK_MIC * * CURRENT SOURCES: * =============== * SOUND_MIXER_OUTSRC - output source * SOUND_MIXER_RECSRC - input source * Operations: * MIXER_READ() and MIXER_WRITE() to control the sources * * VOLUME CONTROL: * =============== * SOUND_MIXER_RECLEV - control the gain level of recording * SOUND_MIXER_VOLUME - control the gain level of playback * MIXER_WRITE and MIXER_READ with each of the device masks will * control the coarse volume control of the device */#define DIR_OUT (0)#define DIR_IN (1<<7)#define OUTPUT_VOLUME (DIR_OUT | 0)#define OUTPUT_STEREO_HEADSET (DIR_OUT | (1 << 0))#define OUTPUT_HANDS_FREE_CLASSD (DIR_OUT | (1 << 1))#define OUTPUT_MONO_EARPIECE (DIR_OUT | (1 << 2))#define OUTPUT_SIDETONE (DIR_OUT | (1 << 3))#define OUTPUT_CARKIT (DIR_OUT | (1 << 4))#define INPUT_VOLUME (DIR_IN | 0)#define INPUT_HEADSET_MIC (DIR_IN | (1 << 0))#define INPUT_MAIN_MIC (DIR_IN | (1 << 1))#define INPUT_SUB_MIC (DIR_IN | (1 << 2))#define INPUT_AUX (DIR_IN | (1 << 3))#define INPUT_CARKIT (DIR_IN | (1 << 4))#define DEFAULT_INPUT_TWL_DEVICE INPUT_HEADSET_MIC#define DEFAULT_INPUT_LNX_DEVICE SOUND_MASK_LINE#define DEFAULT_OUTPUT_TWL_DEVICE OUTPUT_STEREO_HEADSET#define DEFAULT_OUTPUT_LNX_DEVICE SOUND_MASK_LINE1/* Recording devices */#define REC_SRC_MASK (SOUND_MASK_LINE | \ SOUND_MASK_MIC)#define REC_MASK (SOUND_MASK_RECLEV | \ REC_SRC_MASK)/* play back devices */#define OUT_SRC_MASK (SOUND_MASK_LINE1 | \ SOUND_MASK_SPEAKER | \ SOUND_MASK_PHONEOUT)#define OUT_MASK (SOUND_MASK_VOLUME | \ OUT_SRC_MASK)#define DEV_MASK (REC_MASK | \ OUT_MASK)#define DEV_STEREO_DEV (SOUND_MASK_VOLUME | \ SOUND_MASK_RECLEV | \ SOUND_MASK_LINE1 | \ SOUND_MASK_SPEAKER | \ SOUND_MASK_MIC)#define STEREO_MODE (0x1)#define MONO_MODE (0x2)#define MIXER_DEVICE (0x0)#define DSP_DEVICE (0x1)#define AUDIO_MAX_INPUT_VOLUME 100#define AUDIO_MAX_OUTPUT_VOLUME 100#define COMPUTE_PRECISION 100#define AUDIO_INPUT_INCREMENT ((AUDIO_MAX_INPUT_VOLUME * \ COMPUTE_PRECISION)/\ (INPUT_GAIN_MAX))#define AUDIO_OUTPUT_INCREMENT ((AUDIO_MAX_OUTPUT_VOLUME * \ COMPUTE_PRECISION)/\ (OUTPUT_GAIN_MAX))#define AUDIO_DEF_COARSE_VOLUME_LEVEL AUDIO_OUTPUT_COARSE_GAIN_6DB#define MIC_AMP_INCR ((AUDIO_MAX_INPUT_VOLUME * \ COMPUTE_PRECISION)/\ (MICAM_GAIN_MAX))#define ARX_APGA_INCR ((AUDIO_MAX_OUTPUT_VOLUME * \ COMPUTE_PRECISION)/\ (ARX_APGA_MIN))/* EAR/ HS Values */#define NON_LIN_VALS { 3, 2, 1 }#define NON_LIN_GAIN_MAX 3#define NON_LIN_GAIN_MAX_R 2#define NON_LIN_INCREMENT ((AUDIO_MAX_OUTPUT_VOLUME * \ COMPUTE_PRECISION)/\ (NON_LIN_GAIN_MAX_R))#define NON_LIN_MUTE 0#define DEFAULT_OUTPUT_VOLUME 70#define DEFAULT_OUTPUT_SPK_VOLUME 50#define DEFAULT_OUTPUT_HSET_VOLUME 70#define DEFAULT_OUTPUT_EAR_VOLUME 60#define DEFAULT_SIDETONE_VOLUME 20#define DEFAULT_OUTPUT_CARKIT_VOLUME 50#define DEFAULT_INPUT_VOLUME 60#define DEFAULT_INPUT_MIC_VOLUME 80#define DEFAULT_INPUT_LINE_VOLUME 80#define DEFAULT_INPUT_CARKIT_VOLUME 50#define AUDIO_RATE_DEFAULT 8000/* supports only two sample sizes - 16 and 24 */#define AUDIO_SAMPLE_DATA_WIDTH_16 16#define AUDIO_SAMPLE_DATA_WIDTH_24 24 /* From OSS spec: * The least significant * byte gives volume for the left channel and the next 8 bits for * the right channel. */#define READ_LEFT_VOLUME(ARG) ( (ARG) & 0xFF )#define READ_RIGHT_VOLUME(ARG) ( ((ARG) & 0xFF00)>>8 )#define WRITE_LEFT_VOLUME(ARG) ( (ARG) & 0xFF )#define WRITE_RIGHT_VOLUME(ARG) ( ((ARG) & 0xFF)<<8 )#define WRITE_LR_VOLUME(ARG) ( WRITE_RIGHT_VOLUME(ARG) | \ WRITE_LEFT_VOLUME(ARG) )#define CODEC_NAME "TWL4030"#define MIXER_NAME "TWL4030 Mixer"#define PLATFORM_NAME "OMAP3430"/* Define to set the twl as the master w.r.t McBSP * - remove to make mcbsp master */#define TWL_MASTER/* Select the McBSP For Audio */#define AUDIO_MCBSP OMAP2_MCBSP_INTERFACE2#define AUDIO_APLL_DEFAULT APLL_CTL_FREQ_26_0MHZ/***************** MODULE DATA STRUCTURES **/static unsigned int twl4030_rates[] = { 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000};static struct snd_pcm_hw_constraint_list twl4030_pcm_hw_constraint_list = { .count = ARRAY_SIZE(twl4030_rates), .list = twl4030_rates, .mask = 0,};static struct snd_pcm_hardware twl4030_pcm_hardware_playback = { .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), .formats = (SNDRV_PCM_FMTBIT_S16_LE), .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_KNOT), .rate_min = 8000, .rate_max = 48000, .channels_min = 1, .channels_max = 2, .buffer_bytes_max = 128 * 1024,⌨️ 快捷键说明
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