📄 omap2-audio-twl4030.h
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#define BIT_ARXL2PGA_ARXL2PGA_FGAIN (0x000)#define BIT_ARXL2PGA_ARXL2PGA_FGAIN_M (0x0000003F)#define BIT_ARXL2PGA_ARXL2PGA_CGAIN (0x006)#define BIT_ARXL2PGA_ARXL2PGA_CGAIN_M (0x000000C0)/* VRXPGA Fields */#define BIT_VRXPGA_VRXPGA_GAIN (0x000)#define BIT_VRXPGA_VRXPGA_GAIN_M (0x0000003F)/* VSTPGA Fields */#define BIT_VSTPGA_VSTPGA_GAIN (0x000)#define BIT_VSTPGA_VSTPGA_GAIN_M (0x0000003F)#define SIDETONE_MAX_GAIN (0x29)/* VRX2ARXPGA Fields */#define BIT_VRX2ARXPGA_VRX2ARXPGA_GAIN (0x000)#define BIT_VRX2ARXPGA_VRX2ARXPGA_GAIN_M (0x0000001F)/* AVDAC_CTL Fields */#define BIT_AVDAC_CTL_ADACR1_EN (0x000)#define BIT_AVDAC_CTL_ADACR1_EN_M (0x00000001)#define BIT_AVDAC_CTL_ADACL1_EN (0x001)#define BIT_AVDAC_CTL_ADACL1_EN_M (0x00000002)#define BIT_AVDAC_CTL_ADACR2_EN (0x002)#define BIT_AVDAC_CTL_ADACR2_EN_M (0x00000004)#define BIT_AVDAC_CTL_ADACL2_EN (0x003)#define BIT_AVDAC_CTL_ADACL2_EN_M (0x00000008)#define BIT_AVDAC_CTL_VDAC_EN (0x004)#define BIT_AVDAC_CTL_VDAC_EN_M (0x00000010)/* ARX2VTXPGA Fields */#define BIT_ARX2VTXPGA_ARX2VTXPGA_GAIN (0x000)#define BIT_ARX2VTXPGA_ARX2VTXPGA_GAIN_M (0x0000003F)#define ARX_APGA_MIN (0x12)#define ARX_APGA_MAX (0x00)/* ARXL1_APGA_CTL Fields */#define BIT_ARXL1_APGA_CTL_ARXL1_PDZ (0x000)#define BIT_ARXL1_APGA_CTL_ARXL1_PDZ_M (0x00000001)#define BIT_ARXL1_APGA_CTL_ARXL1_DA_EN (0x001)#define BIT_ARXL1_APGA_CTL_ARXL1_DA_EN_M (0x00000002)#define BIT_ARXL1_APGA_CTL_ARXL1_FM_EN (0x002)#define BIT_ARXL1_APGA_CTL_ARXL1_FM_EN_M (0x00000004)#define BIT_ARXL1_APGA_CTL_ARXL1_GAIN_SET (0x003)#define BIT_ARXL1_APGA_CTL_ARXL1_GAIN_SET_M (0x000000F8)/* ARXR1_APGA_CTL Fields */#define BIT_ARXR1_APGA_CTL_ARXR1_PDZ (0x000)#define BIT_ARXR1_APGA_CTL_ARXR1_PDZ_M (0x00000001)#define BIT_ARXR1_APGA_CTL_ARXR1_DA_EN (0x001)#define BIT_ARXR1_APGA_CTL_ARXR1_DA_EN_M (0x00000002)#define BIT_ARXR1_APGA_CTL_ARXR1_FM_EN (0x002)#define BIT_ARXR1_APGA_CTL_ARXR1_FM_EN_M (0x00000004)#define BIT_ARXR1_APGA_CTL_ARXR1_GAIN_SET (0x003)#define BIT_ARXR1_APGA_CTL_ARXR1_GAIN_SET_M (0x000000F8)/* ARXL2_APGA_CTL Fields */#define BIT_ARXL2_APGA_CTL_ARXL2_PDZ (0x000)#define BIT_ARXL2_APGA_CTL_ARXL2_PDZ_M (0x00000001)#define BIT_ARXL2_APGA_CTL_ARXL2_DA_EN (0x001)#define BIT_ARXL2_APGA_CTL_ARXL2_DA_EN_M (0x00000002)#define BIT_ARXL2_APGA_CTL_ARXL2_FM_EN (0x002)#define BIT_ARXL2_APGA_CTL_ARXL2_FM_EN_M (0x00000004)#define BIT_ARXL2_APGA_CTL_ARXL2_GAIN_SET (0x003)#define BIT_ARXL2_APGA_CTL_ARXL2_GAIN_SET_M (0x000000F8)/* ARXR2_APGA_CTL Fields */#define BIT_ARXR2_APGA_CTL_ARXR2_PDZ (0x000)#define BIT_ARXR2_APGA_CTL_ARXR2_PDZ_M (0x00000001)#define BIT_ARXR2_APGA_CTL_ARXR2_DA_EN (0x001)#define BIT_ARXR2_APGA_CTL_ARXR2_DA_EN_M (0x00000002)#define BIT_ARXR2_APGA_CTL_ARXR2_FM_EN (0x002)#define BIT_ARXR2_APGA_CTL_ARXR2_FM_EN_M (0x00000004)#define BIT_ARXR2_APGA_CTL_ARXR2_GAIN_SET (0x003)#define BIT_ARXR2_APGA_CTL_ARXR2_GAIN_SET_M (0x000000F8)/* ATX2ARXPGA Fields */#define BIT_ATX2ARXPGA_ATX2ARXR_PGA (0x000)#define BIT_ATX2ARXPGA_ATX2ARXR_PGA_M (0x00000007)#define BIT_ATX2ARXPGA_ATX2ARXL_PGA (0x003)#define BIT_ATX2ARXPGA_ATX2ARXL_PGA_M (0x00000038)/* BT_IF Fields */#define BIT_BT_IF_BT_EN (0x000)#define BIT_BT_IF_BT_EN_M (0x00000001)#define BIT_BT_IF_BT_TRI_EN (0x002)#define BIT_BT_IF_BT_TRI_EN_M (0x00000004)#define BIT_BT_IF_BT_SWAP (0x004)#define BIT_BT_IF_BT_SWAP_M (0x00000010)#define BIT_BT_IF_BT_DOUT_EN (0x005)#define BIT_BT_IF_BT_DOUT_EN_M (0x00000020)#define BIT_BT_IF_BT_DIN_EN (0x006)#define BIT_BT_IF_BT_DIN_EN_M (0x00000040)#define BIT_BT_IF_SPARE (0x007)#define BIT_BT_IF_SPARE_M (0x00000080)/* BTPGA Fields */#define BIT_BTPGA_BTRXPGA_GAIN (0x000)#define BIT_BTPGA_BTRXPGA_GAIN_M (0x0000000F)#define BIT_BTPGA_BTTXPGA_GAIN (0x004)#define BIT_BTPGA_BTTXPGA_GAIN_M (0x000000F0)/* BTSTPGA Fields */#define BIT_BTSTPGA_BTSTPGA_GAIN (0x000)#define BIT_BTSTPGA_BTSTPGA_GAIN_M (0x0000003F)/* EAR_CTL Fields */#define BIT_EAR_CTL_EAR_VOICE_EN (0x000)#define BIT_EAR_CTL_EAR_VOICE_EN_M (0x00000001)#define BIT_EAR_CTL_EAR_AL1_EN (0x001)#define BIT_EAR_CTL_EAR_AL1_EN_M (0x00000002)#define BIT_EAR_CTL_EAR_AL2_EN (0x002)#define BIT_EAR_CTL_EAR_AL2_EN_M (0x00000004)#define BIT_EAR_CTL_EAR_AR1_EN (0x003)#define BIT_EAR_CTL_EAR_AR1_EN_M (0x00000008)#define BIT_EAR_CTL_EAR_GAIN (0x004)#define BIT_EAR_CTL_EAR_GAIN_M (0x00000030)#define BIT_EAR_CTL_SPARE (0x006)#define BIT_EAR_CTL_SPARE_M (0x00000040)#define BIT_EAR_CTL_EAR_OUTLOW_EN (0x007)#define BIT_EAR_CTL_EAR_OUTLOW_EN_M (0x00000080)/* HS_GAIN_SET Fields */#define BIT_HS_GAIN_SET_HSL_GAIN (0x000)#define BIT_HS_GAIN_SET_HSL_GAIN_M (0x00000003)#define BIT_HS_GAIN_SET_HSR_GAIN (0x002)#define BIT_HS_GAIN_SET_HSR_GAIN_M (0x0000000C)#define BIT_HS_GAIN_SET_SPARE (0x006)#define BIT_HS_GAIN_SET_SPARE_M (0x00000040)/* HS_SEL Fields */#define BIT_HS_SEL_HSOL_VOICE_EN (0x000)#define BIT_HS_SEL_HSOL_VOICE_EN_M (0x00000001)#define BIT_HS_SEL_HSOL_AL1_EN (0x001)#define BIT_HS_SEL_HSOL_AL1_EN_M (0x00000002)#define BIT_HS_SEL_HSOL_AL2_EN (0x002)#define BIT_HS_SEL_HSOL_AL2_EN_M (0x00000004)#define BIT_HS_SEL_HSOR_VOICE_EN (0x003)#define BIT_HS_SEL_HSOR_VOICE_EN_M (0x00000008)#define BIT_HS_SEL_HSOR_AR1_EN (0x004)#define BIT_HS_SEL_HSOR_AR1_EN_M (0x00000010)#define BIT_HS_SEL_HSOR_AR2_EN (0x005)#define BIT_HS_SEL_HSOR_AR2_EN_M (0x00000020)#define BIT_HS_SEL_HS_OUTLOW_EN (0x006)#define BIT_HS_SEL_HS_OUTLOW_EN_M (0x00000040)#define BIT_HS_SEL_HSR_INV_EN (0x007)#define BIT_HS_SEL_HSR_INV_EN_M (0x00000080)/* HS_POPN_SET Fields */#define BIT_HS_POPN_SET_RAMP_EN (0x001)#define BIT_HS_POPN_SET_RAMP_EN_M (0x00000002)#define BIT_HS_POPN_SET_RAMP_DELAY (0x002)#define BIT_HS_POPN_SET_RAMP_DELAY_M (0x0000001C)#define BIT_HS_POPN_SET_EXTMUTE (0x005)#define BIT_HS_POPN_SET_EXTMUTE_M (0x00000020)#define BIT_HS_POPN_SET_VMID_EN (0x006)#define BIT_HS_POPN_SET_VMID_EN_M (0x00000040)/* PREDL_CTL Fields */#define BIT_PREDL_CTL_PREDL_VOICE_EN (0x000)#define BIT_PREDL_CTL_PREDL_VOICE_EN_M (0x00000001)#define BIT_PREDL_CTL_PREDL_AL1_EN (0x001)#define BIT_PREDL_CTL_PREDL_AL1_EN_M (0x00000002)#define BIT_PREDL_CTL_PREDL_AL2_EN (0x002)#define BIT_PREDL_CTL_PREDL_AL2_EN_M (0x00000004)#define BIT_PREDL_CTL_PREDL_AR2_EN (0x003)#define BIT_PREDL_CTL_PREDL_AR2_EN_M (0x00000008)#define BIT_PREDL_CTL_PREDL_GAIN (0x004)#define BIT_PREDL_CTL_PREDL_GAIN_M (0x00000030)#define BIT_PREDL_CTL_PREDL_OUTLOW_EN (0x007)#define BIT_PREDL_CTL_PREDL_OUTLOW_EN_M (0x00000080)/* PREDR_CTL Fields */#define BIT_PREDR_CTL_PREDR_VOICE_EN (0x000)#define BIT_PREDR_CTL_PREDR_VOICE_EN_M (0x00000001)#define BIT_PREDR_CTL_PREDR_AR1_EN (0x001)#define BIT_PREDR_CTL_PREDR_AR1_EN_M (0x00000002)#define BIT_PREDR_CTL_PREDR_AR2_EN (0x002)#define BIT_PREDR_CTL_PREDR_AR2_EN_M (0x00000004)#define BIT_PREDR_CTL_PREDR_AL2_EN (0x003)#define BIT_PREDR_CTL_PREDR_AL2_EN_M (0x00000008)#define BIT_PREDR_CTL_PREDR_GAIN (0x004)#define BIT_PREDR_CTL_PREDR_GAIN_M (0x00000030)#define BIT_PREDR_CTL_PREDR_OUTLOW_EN (0x007)#define BIT_PREDR_CTL_PREDR_OUTLOW_EN_M (0x00000080)/* PRECKL_CTL Fields */#define BIT_PRECKL_CTL_PRECKL_VOICE_EN (0x000)#define BIT_PRECKL_CTL_PRECKL_VOICE_EN_M (0x00000001)#define BIT_PRECKL_CTL_PRECKL_AL1_EN (0x001)#define BIT_PRECKL_CTL_PRECKL_AL1_EN_M (0x00000002)#define BIT_PRECKL_CTL_PRECKL_AL2_EN (0x002)#define BIT_PRECKL_CTL_PRECKL_AL2_EN_M (0x00000004)#define BIT_PRECKL_CTL_PRECKL_GAIN (0x004)#define BIT_PRECKL_CTL_PRECKL_GAIN_M (0x00000030)#define BIT_PRECKL_CTL_PRECKL_EN (0x006)#define BIT_PRECKL_CTL_PRECKL_EN_M (0x00000040)/* PRECKR_CTL Fields */#define BIT_PRECKR_CTL_PRECKR_VOICE_EN (0x000)#define BIT_PRECKR_CTL_PRECKR_VOICE_EN_M (0x00000001)#define BIT_PRECKR_CTL_PRECKR_AR1_EN (0x001)#define BIT_PRECKR_CTL_PRECKR_AR1_EN_M (0x00000002)#define BIT_PRECKR_CTL_PRECKR_AR2_EN (0x002)#define BIT_PRECKR_CTL_PRECKR_AR2_EN_M (0x00000004)#define BIT_PRECKR_CTL_PRECKR_GAIN (0x004)#define BIT_PRECKR_CTL_PRECKR_GAIN_M (0x00000030)#define BIT_PRECKR_CTL_PRECKR_EN (0x006)#define BIT_PRECKR_CTL_PRECKR_EN_M (0x00000040)#define HANDS_FREEL_VOICE (0x0)#define HANDS_FREEL_AL1 (0x1)#define HANDS_FREEL_AL2 (0x2)#define HANDS_FREEL_AR2 (0x3)#define HANDS_FREER_VOICE (0x0)#define HANDS_FREER_AR1 (0x1)#define HANDS_FREER_AR2 (0x2)#define HANDS_FREER_AL2 (0x3)/* HFL_CTL Fields */#define BIT_HFL_CTL_HFL_INPUT_SEL (0x000)#define BIT_HFL_CTL_HFL_INPUT_SEL_M (0x00000003)#define BIT_HFL_CTL_HFL_HB_EN (0x002)#define BIT_HFL_CTL_HFL_HB_EN_M (0x00000004)#define BIT_HFL_CTL_HFL_LOOP_EN (0x003)#define BIT_HFL_CTL_HFL_LOOP_EN_M (0x00000008)#define BIT_HFL_CTL_HFL_RAMP_EN (0x004)#define BIT_HFL_CTL_HFL_RAMP_EN_M (0x00000010)#define BIT_HFL_CTL_HFL_REF_EN (0x005)#define BIT_HFL_CTL_HFL_REF_EN_M (0x00000020)/* HFR_CTL Fields */#define BIT_HFR_CTL_HFR_INPUT_SEL (0x000)#define BIT_HFR_CTL_HFR_INPUT_SEL_M (0x00000003)#define BIT_HFR_CTL_HFR_HB_EN (0x002)#define BIT_HFR_CTL_HFR_HB_EN_M (0x00000004)#define BIT_HFR_CTL_HFR_LOOP_EN (0x003)#define BIT_HFR_CTL_HFR_LOOP_EN_M (0x00000008)#define BIT_HFR_CTL_HFR_RAMP_EN (0x004)#define BIT_HFR_CTL_HFR_RAMP_EN_M (0x00000010)#define BIT_HFR_CTL_HFR_REF_EN (0x005)#define BIT_HFR_CTL_HFR_REF_EN_M (0x00000020)/* ALC_CTL Fields */#define BIT_ALC_CTL_ALC_WAIT (0x000)#define BIT_ALC_CTL_ALC_WAIT_M (0x00000007)#define BIT_ALC_CTL_MAINMIC_ALC_EN (0x003)#define BIT_ALC_CTL_MAINMIC_ALC_EN_M (0x00000008)#define BIT_ALC_CTL_SUBMIC_ALC_EN (0x004)#define BIT_ALC_CTL_SUBMIC_ALC_EN_M (0x00000010)#define BIT_ALC_CTL_ALC_MODE (0x005)#define BIT_ALC_CTL_ALC_MODE_M (0x00000020)#define BIT_ALC_CTL_SPARE1 (0x006)#define BIT_ALC_CTL_SPARE1_M (0x00000040)#define BIT_ALC_CTL_SPARE2 (0x007)#define BIT_ALC_CTL_SPARE2_M (0x00000080)/* ALC_SET1 Fields */#define BIT_ALC_SET1_ALC_MIN_LIMIT (0x000)#define BIT_ALC_SET1_ALC_MIN_LIMIT_M (0x00000007)#define BIT_ALC_SET1_ALC_MAX_LIMIT (0x003)#define BIT_ALC_SET1_ALC_MAX_LIMIT_M (0x00000038)/* ALC_SET2 Fields */#define BIT_ALC_SET2_ALC_RELEASE (0x000)#define BIT_ALC_SET2_ALC_RELEASE_M (0x00000007)#define BIT_ALC_SET2_ALC_ATTACK (0x003)#define BIT_ALC_SET2_ALC_ATTACK_M (0x00000038)#define BIT_ALC_SET2_ALC_STEP (0x006)#define BIT_ALC_SET2_ALC_STEP_M (0x00000040)/* BOOST_CTL Fields */#define BIT_BOOST_CTL_EFFECT (0x000)#define BIT_BOOST_CTL_EFFECT_M (0x00000003)/* SOFTVOL_CTL Fields */#define BIT_SOFTVOL_CTL_SOFTVOL_EN (0x000)#define BIT_SOFTVOL_CTL_SOFTVOL_EN_M (0x00000001)#define BIT_SOFTVOL_CTL_SOFTVOL_SET (0x005)#define BIT_SOFTVOL_CTL_SOFTVOL_SET_M (0x000000E0)/* DTMF_FREQSEL Fields */#define BIT_DTMF_FREQSEL_FREQSEL (0x000)#define BIT_DTMF_FREQSEL_FREQSEL_M (0x0000001F)#define BIT_DTMF_FREQSEL_SPARE1 (0x006)#define BIT_DTMF_FREQSEL_SPARE1_M (0x00000040)#define BIT_DTMF_FREQSEL_SPARE2 (0x007)#define BIT_DTMF_FREQSEL_SPARE2_M (0x00000080)/* DTMF_TONEXT1H Fields */#define BIT_DTMF_TONEXT1H_EXT_TONE1H (0x000)#define BIT_DTMF_TONEXT1H_EXT_TONE1H_M (0x000000FF)/* DTMF_TONEXT1L Fields */#define BIT_DTMF_TONEXT1L_EXT_TONE1L (0x000)#define BIT_DTMF_TONEXT1L_EXT_TONE1L_M (0x000000FF)/* DTMF_TONEXT2H Fields */#define BIT_DTMF_TONEXT2H_EXT_TONE2H (0x000)#define BIT_DTMF_TONEXT2H_EXT_TONE2H_M (0x000000FF)/* DTMF_TONEXT2L Fields */#define BIT_DTMF_TONEXT2L_EXT_TONE2L (0x000)#define BIT_DTMF_TONEXT2L_EXT_TONE2L_M (0x000000FF)/* DTMF_TONOFF Fields */#define BIT_DTMF_TONOFF_TONE_ON_TIME (0x000)#define BIT_DTMF_TONOFF_TONE_ON_TIME_M (0x0000000F)#define BIT_DTMF_TONOFF_TONE_OFF_TIME (0x004)#define BIT_DTMF_TONOFF_TONE_OFF_TIME_M (0x000000F0)/* DTMF_WANONOFF Fields */#define BIT_DTMF_WANONOFF_WAMBLE_ON_TIME (0x000)#define BIT_DTMF_WANONOFF_WAMBLE_ON_TIME_M (0x0000000F)#define BIT_DTMF_WANONOFF_WAMBLE_OFF_TIME (0x004)#define BIT_DTMF_WANONOFF_WAMBLE_OFF_TIME_M (0x000000F0)/* I2S_RX_SCRAMBLE_H Fields */#define BIT_I2S_RX_SCRAMBLE_H_I2S_RX_SCRAMBLE_H (0x000)#define BIT_I2S_RX_SCRAMBLE_H_I2S_RX_SCRAMBLE_H_M (0x000000FF)/* I2S_RX_SCRAMBLE_M Fields */#define BIT_I2S_RX_SCRAMBLE_M_I2S_RX_SCRAMBLE_M (0x000)#define BIT_I2S_RX_SCRAMBLE_M_I2S_RX_SCRAMBLE_M_M (0x000000FF)/* I2S_RX_SCRAMBLE_L Fields */#define BIT_I2S_RX_SCRAMBLE_L_I2S_RX_SCRAMBLE_L (0x000)#define BIT_I2S_RX_SCRAMBLE_L_I2S_RX_SCRAMBLE_L_M (0x000000FF)/* APLL_CTL Fields */⌨️ 快捷键说明
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