display.h

omap3 linux 2.6 用nocc去除了冗余代码

#define VENC_L21_WC_CTL				0x005C
#define VENC_HTRIGGER_VTRIGGER			0x0060
#define VENC_SAVID_EAVID			0x0064
#define VENC_FLEN_FAL				0x0068
#define VENC_LAL_PHASE_RESET			0x006C
#define VENC_HS_INT_START_STOP_X		0x0070
#define VENC_HS_EXT_START_STOP_X		0x0074
#define VENC_VS_INT_START_X			0x0078
#define VENC_VS_INT_STOP_X_VS_INT_START_Y	0x007C
#define VENC_VS_INT_STOP_Y_VS_EXT_START_X	0x0080
#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y	0x0084
#define VENC_VS_EXT_STOP_Y			0x0088
#define VENC_AVID_START_STOP_X			0x0090
#define VENC_AVID_START_STOP_Y			0x0094
#define VENC_FID_INT_START_X_FID_INT_START_Y	0x00A0
#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X	0x00A4
#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y	0x00A8
#define VENC_TVDETGP_INT_START_STOP_X		0x00B0
#define VENC_TVDETGP_INT_START_STOP_Y		0x00B4
#define VENC_GEN_CTRL				0x00B8
#define VENC_DAC_TST				0x00C4
#define VENC_DAC				0x00C8

/* VENC bit fields */
#define VENC_FCONTROL_RESET			(1<<8)

/* Rotation using VRFB */
#define SMS_ROT_VIRT_BASE(context, degree)	0x70000000 		\
						| 0x4000000 * (context)	\
						| 0x1000000 * (degree/90)
#define	SMS_IMAGEHEIGHT_OFFSET			16
#define	SMS_IMAGEWIDTH_OFFSET			0
#define	SMS_PH_OFFSET				8
#define	SMS_PW_OFFSET				4
#define	SMS_PS_OFFSET				0

#define OMAP_SMS_BASE	SMS_PHYS

#define	SMS_ROT0_PHYSICAL_BA(context)	__REG32(OMAP_SMS_BASE + 0x188 \
						+ 0x10 * context)
#define	SMS_ROT_CONTROL(context)	__REG32(OMAP_SMS_BASE + 0x180 \
						+ 0x10 * context)
#define	SMS_ROT0_SIZE(context)		__REG32(OMAP_SMS_BASE + 0x184 \
						+ 0x10 * context)

/* Structure to store and restore the DSS registers */
struct omap24xx_dispc_regs
{
	u32 revision;			/* 0x000 */
	u32 res1[3];
	u32 sysconfig;		/* 0x010 */
	u32 sysstatus;		/* 0x014 */
	u32 irqstatus;		/* 0x018 */
	u32 irqenable;		/* 0x01C */
	u32 res2[8];
	u32 control;			/* 0x040 */
	u32 config;			/* 0x044 */
	u32 capable;			/* 0x048 */
	u32 default_color0;		/* 0x04C */
	u32 default_color1;		/* 0x050 */
	u32 trans_color0;		/* 0x054 */
	u32 trans_color1;		/* 0x058 */
	u32 line_status;		/* 0x05C */
	u32 line_number;		/* 0x060 */
	u32 timing_h;			/* 0x064 */
	u32 timing_v;			/* 0x068 */
	u32 pol_freq;			/* 0x06C */
	u32 divisor;			/* 0x070 */
	u32 global_alpha;		/* 0x074 */
	u32 size_dig;			/* 0x078 */
	u32 size_lcd;			/* 0x07C */
	u32 gfx_ba0;			/* 0x080 */
	u32 gfx_ba1;			/* 0x084 */
	u32 gfx_position;		/* 0x088 */
	u32 gfx_size;			/* 0x08C */
	u32 res4[4];
	u32 gfx_attributes;		/* 0x0A0 */
	u32 gfx_fifo_threshold;	/* 0x0A4 */
	u32 gfx_fifo_size;		/* 0x0A8 */
	u32 gfx_row_inc;		/* 0x0AC */
	u32 gfx_pixel_inc;		/* 0x0B0 */
	u32 gfx_window_skip;		/* 0x0B4 */
	u32 gfx_table_ba;		/* 0x0B8 */
	u32 vid1_ba0;			/* 0x0BC */
	u32 vid1_ba1;			/* 0x0C0 */
	u32 vid1_position;		/* 0x0C4 */
	u32 vid1_size;		/* 0x0C8 */
	u32 vid1_attributes;		/* 0x0CC */
	u32 vid1_fifo_threshold;	/* 0x0D0 */
	u32 vid1_fifo_size;		/* 0x0D4 */
	u32 vid1_row_inc;		/* 0x0D8 */
	u32 vid1_pixel_inc;		/* 0x0DC */
	u32 vid1_fir;			/* 0x0E0 */
	u32 vid1_picture_size;	/* 0x0E4 */
	u32 vid1_accu0;		/* 0x0E8 */
	u32 vid1_accu1;		/* 0x0EC */
	u32 vid1_fir_coef_h0;		/* 0x0F0 */
	u32 vid1_fir_coef_hv0;	/* 0x0F4 */
	u32 vid1_fir_coef_h1;		/* 0x0F8 */
	u32 vid1_fir_coef_hv1;	/* 0x0FC */
	u32 vid1_fir_coef_h2;		/* 0x100 */
	u32 vid1_fir_coef_hv2;	/* 0x104 */
	u32 vid1_fir_coef_h3;		/* 0x108 */
	u32 vid1_fir_coef_hv3;	/* 0x10C */
	u32 vid1_fir_coef_h4;		/* 0x110 */
	u32 vid1_fir_coef_hv4;	/* 0x114 */
	u32 vid1_fir_coef_h5;		/* 0x118 */
	u32 vid1_fir_coef_hv5;	/* 0x11C */
	u32 vid1_fir_coef_h6;		/* 0x120 */
	u32 vid1_fir_coef_hv6;	/* 0x124 */
	u32 vid1_fir_coef_h7;		/* 0x128 */
	u32 vid1_fir_coef_hv7;	/* 0x12C */
	u32 vid1_conv_coef0;		/* 0x130 */
	u32 vid1_conv_coef1;		/* 0x134 */
	u32 vid1_conv_coef2;		/* 0x138 */
	u32 vid1_conv_coef3;		/* 0x13C */
	u32 vid1_conv_coef4;		/* 0x140 */
	u32 res5[2];
	u32 vid2_ba0;			/* 0x14C */
	u32 vid2_ba1;			/* 0x150 */
	u32 vid2_position;		/* 0x154 */
	u32 vid2_size;		/* 0x158 */
	u32 vid2_attributes;		/* 0x15C */
	u32 vid2_fifo_threshold;	/* 0x160 */
	u32 vid2_fifo_size;		/* 0x164 */
	u32 vid2_row_inc;		/* 0x168 */
	u32 vid2_pixel_inc;		/* 0x16C */
	u32 vid2_fir;			/* 0x170 */
	u32 vid2_picture_size;	/* 0x174 */
	u32 vid2_accu0;		/* 0x178 */
	u32 vid2_accu1;		/* 0x17C */
	u32 vid2_fir_coef_h0;		/* 0x180 */
	u32 vid2_fir_coef_hv0;	/* 0x184 */
	u32 vid2_fir_coef_h1;		/* 0x188 */
	u32 vid2_fir_coef_hv1;	/* 0x18C */
	u32 vid2_fir_coef_h2;		/* 0x190 */
	u32 vid2_fir_coef_hv2;	/* 0x194 */
	u32 vid2_fir_coef_h3;		/* 0x198 */
	u32 vid2_fir_coef_hv3;	/* 0x19C */
	u32 vid2_fir_coef_h4;		/* 0x1A0 */
	u32 vid2_fir_coef_hv4;	/* 0x1A4 */
	u32 vid2_fir_coef_h5;		/* 0x1A8 */
	u32 vid2_fir_coef_hv5;	/* 0x1AC */
	u32 vid2_fir_coef_h6;		/* 0x1B0 */
	u32 vid2_fir_coef_hv6;	/* 0x1B4 */
	u32 vid2_fir_coef_h7;		/* 0x1B8 */
	u32 vid2_fir_coef_hv7;	/* 0x1BC */
	u32 vid2_conv_coef0;		/* 0x1C0 */
	u32 vid2_conv_coef1;		/* 0x1C4 */
	u32 vid2_conv_coef2;		/* 0x1C8 */
	u32 vid2_conv_coef3;		/* 0x1CC */
	u32 vid2_conv_coef4;		/* 0x1D0 */
	u32 data_cycle1;		/* 0x1D4 */
	u32 data_cycle2;		/* 0x1D8 */
	u32 data_cycle3;		/* 0x1DC */
	/* omap3430 specific registers */
	u32 vid1_fir_coef_v0;		/* 0x1E0 */
	u32 vid1_fir_coef_v1;		/* 0x1E4 */
	u32 vid1_fir_coef_v2;		/* 0x1E8 */
	u32 vid1_fir_coef_v3;		/* 0x1EC */
	u32 vid1_fir_coef_v4;		/* 0x1F0 */
	u32 vid1_fir_coef_v5;		/* 0x1F4 */
	u32 vid1_fir_coef_v6;		/* 0x1F8 */
	u32 vid1_fir_coef_v7;		/* 0x1FC */
	u32 vid2_fir_coef_v0;		/* 0x200 */
	u32 vid2_fir_coef_v1;		/* 0x204 */
	u32 vid2_fir_coef_v2;		/* 0x208 */
	u32 vid2_fir_coef_v3;		/* 0x20C */
	u32 vid2_fir_coef_v4;		/* 0x210 */
	u32 vid2_fir_coef_v5;		/* 0x214 */
	u32 vid2_fir_coef_v6;		/* 0x218 */
	u32 vid2_fir_coef_v7;		/* 0x21C */
	u32 cpr_coef_r;			/* 0x220 */
	u32 cpr_coef_g;			/* 0x224 */
	u32 cpr_coef_b;			/* 0x228 */
	u32 gfx_preload;		/* 0x22C */
	u32 vid1_preload;		/* 0x230 */
	u32 vid2_preload;		/* 0x234 */
};

/* WARN: read-only registers omitted! */
struct omap_dss_regs {
	u32 sysconfig;
	u32 control;
	u32 sdi_control;
	u32 pll_control;
	struct omap24xx_dispc_regs dispc;
};

struct tvlcd_status_t {
	int ltype;
	int output_dev;
	int status;
}; 

/* color space conversion matrices */
const static short int cc_bt601[3][3] = { {298, 409, 0},
{298, -208, -100},
{298, 0, 517}
};
const static short int cc_bt709[3][3] = { {298, 459, 0},
{298, -137, -55},
{298, 0, 541}
};
const static short int cc_bt601_full[3][3] = { {256, 351, 0},
{256, -179, -86},
{256, 0, 443}
};

/*----------- following are exposed values and APIs -------------------------*/

#define OMAP2_GRAPHICS		0
#define OMAP2_VIDEO1		1
#define OMAP2_VIDEO2		2
#define OMAP_DSS_GENERIC	3
#define OMAP_DSS_DISPC_GENERIC	4
#define DSS_CTX_NUMBER		(OMAP_DSS_DISPC_GENERIC + 1)

#define OMAP2_OUTPUT_LCD	4
#define OMAP2_OUTPUT_TV		5

/* Dithering enable/disable */
#define DITHERING_ON		28
#define DITHERING_OFF		29

/* TVOUT Definitions */
enum omap2_tvstandard {	
	PAL_BDGHI = 0,
	PAL_NC,
	PAL_N,
	PAL_M,
	PAL_60,
	NTSC_M,
	NTSC_J,
	NTSC_443,
};

/* TV ref ON/OFF */
#define TVREF_ON		30
#define TVREF_OFF		31

/* LCD data lines configuration */
#define LCD_DATA_LINE_12BIT     32
#define LCD_DATA_LINE_16BIT     33
#define LCD_DATA_LINE_18BIT     34
#define LCD_DATA_LINE_24BIT     35

/* transparent color key types */
#define OMAP2_GFX_DESTINATION 	100
#define OMAP2_VIDEO_SOURCE	101

/* SDRAM page size parameters used for VRFB settings */
#define PAGE_WIDTH_EXP		5	/* page width = 1 << PAGE_WIDTH_EXP */
#define PAGE_HEIGHT_EXP		5	/* page height = 1 << PAGE_HEIGHT_EXP */

/* 2048 x 2048 is max res supported by OMAP24xx display controller */
#define MAX_PIXELS_PER_LINE	2048
#define MAX_LINES		2048

#define TV_OFF		   	0
#define TV_ON		   	1
#define LCD_OFF			0
#define LCD_ON			1

/* States needed for TV-LCD on the fly */
#define TVLCD_STOP		1
#define TVLCD_CONTINUE		2

/* VRFB offset computation parameters */
#define SIDE_H          1
#define SIDE_W          0


/* GFX FIFO thresholds */
#define RMODE_GFX_FIFO_HIGH_THRES       0x3FC
#define RMODE_GFX_FIFO_LOW_THRES        0x3BC

extern short int current_colorconv_values[2][3][3];

/* input layer APIs */
extern int omap2_disp_request_layer (int ltype);
extern void omap2_disp_release_layer (int ltype);
extern void omap2_disp_disable_layer (int ltype);
extern void omap2_disp_enable_layer (int ltype);
extern void omap2_disp_config_vlayer (int ltype, struct v4l2_pix_format *pix,
					struct v4l2_rect *crop,
					struct v4l2_window *win,
					int rotation_deg, int mirroring);
extern int omap2_disp_reg_sync_bit(int output_dev);
extern void omap2_disp_config_gfxlayer (u32 size_x, u32 size_y,
					int color_depth);
extern void omap2_disp_start_vlayer (int ltype, struct v4l2_pix_format *pix,
					struct v4l2_rect *crop, struct v4l2_window *win,
					unsigned long fb_base_phys,
					int rotation_deg, int mirroring);
extern void omap2_disp_start_gfxlayer (void);

/* output device APIs */
extern void omap2_disp_get_panel_size (int output_dev, int *witdth,
					int *height);
extern void omap2_disp_set_panel_size (int output_dev, int witdth,
					int height);
extern void omap2_disp_disable_output_dev (int output_dev);
extern void omap2_disp_enable_output_dev (int output_dev);
extern void omap2_disp_config_lcd (u32 clkdiv, u32 hbp, u32 hfp, u32 hsw,
		u32 vbp, u32 vfp, u32 vsw);
extern void omap2_disp_lcdcfg_polfreq(u32 hsync_high, u32 vsync_high,
		u32 acb,u32 ipc, u32 onoff);
extern void omap2_disp_set_pcd (u32 pcd);
extern void omap2_disp_set_dssfclk (void);
extern void omap2_disp_set_tvstandard (int tvstandard);
extern int omap2_disp_get_tvstandard (void);
extern void omap2_disp_get_tvlcd(struct tvlcd_status_t *status);
extern void omap2_disp_set_tvlcd(int status);
extern void omap2_disp_set_dithering (int dither_state);
extern void omap2_disp_set_tvref (int tvref_state);
extern int omap2_disp_get_dithering (void);

extern void omap2_disp_set_lcddatalines (int no_of_lines);
extern int omap2_disp_get_lcddatalines (void);

/* connection of input layers to output devices */
extern int omap2_disp_get_output_dev (int ltype);
extern void omap2_disp_set_output_dev (int ltype, int output_dev);
extern void omap2_disp_set_dma_params (int ltype, int output_dev,
					u32 ba0, u32 ba1, u32 row_inc,
					u32 pix_inc);

/* DSS power management */
extern void omap2_disp_get_dss (void);
extern void omap2_disp_put_dss (void);


/* Color conversion */
void omap2_disp_set_default_colorconv (int ltype,
					struct v4l2_pix_format *pix);
void omap2_disp_set_colorconv (int ltype, struct v4l2_pix_format *pix);

/* background color */
extern void omap2_disp_set_bg_color (int output_dev, int color);
extern void omap2_disp_get_bg_color (int output_dev, int *color);

/* transparent color key */
extern void omap2_disp_set_colorkey (int output_dev, int key_type,
					int key_val);
extern void omap2_disp_get_colorkey (int output_dev, int *key_type,
					int *key_val);
extern void omap2_disp_enable_colorkey (int output_dev);
extern void omap2_disp_disable_colorkey (int output_dev);

/* alpha blending */
int omap2_disp_get_alphablend(int output_dev);
void omap2_disp_set_alphablend(int output_dev,int value);
unsigned char omap2_disp_get_global_alphablend_value(int ltype);
void omap2_disp_set_global_alphablend_value(int ltype,int value);

/* other helpers */
extern void omap2_disp_set_gfx_palette (u32 palette_ba);
extern void omap2_disp_pixels_per_clock (unsigned int *nom,
					 unsigned int *den);

/* rotation APIs */
extern int omap2_disp_set_vrfb (int context, u32 phy_addr,
				u32 width, u32 height, u32 bytes_per_pixel);

/* display controller register synchronization */
void omap2_disp_reg_sync (int output_dev);
extern int omap2_disp_reg_sync_done (int output_dev);

/* disable LCD and TV outputs and sync with next frame */
extern void omap2_disp_disable (unsigned long timeout_ticks);

/* interrupt handling */
typedef void (*omap2_disp_isr_t) (void *arg, struct pt_regs * regs, u32 irqstatus);
extern int omap2_disp_register_isr (omap2_disp_isr_t isr, void *arg,
					unsigned int mask);
extern int omap2_disp_unregister_isr (omap2_disp_isr_t isr);
extern int omap2_disp_irqenable(omap2_disp_isr_t isr,unsigned int mask);
extern int omap2_disp_irqdisable(omap2_disp_isr_t isr,unsigned int mask);
extern void omap2_disp_save_initstate (int layer);
extern void omap2_disp_restore_initstate (int layer);

/* LPR */
int omap2_disp_lpr_enable(void);
int omap2_disp_lpr_disable(void);
int omap2_disp_get_gfx_fifo_low_threshold(void);
void omap2_disp_set_gfx_fifo_low_threshold(int thrs);
int omap2_disp_get_gfx_fifo_high_threshold(void);
void omap2_disp_set_gfx_fifo_high_threshold(int thrs); 

/* clk functions */
extern void omap2_disp_put_all_clks(void);
extern void omap2_disp_get_all_clks(void);

extern void omap2_disp_power_on_tv(void);

extern int omap2_disp_get_vrfb_offset(u32, u32, int);

extern void omap2_disp_start_video_layer(int);

extern void omap2_disp_set_addr(int ltype, u32 lcd_phys_addr, u32 tv_phys_addr_f0, u32 tv_phys_addr_f1);

/*------------------ end of exposed values and APIs -------------------------*/