📄 omap24xx-uart.h
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/* * linux/include/asm-arm/arch-omap24xx/omap24xx-uart.h * * register definitions for omap24xx uart controller. * * Copyright (C) 2004-2005 Texas Instruments, Inc. * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. */#define __OMAP24XX_UART_H__#include <asm/arch/hardware.h>struct uart_config { u8 mode; u8 mdr1; /* Mode registers */ u8 mdr2; u8 dll; /* divisor registers - generates baudrates */ u8 dlh; u8 mcr; /* Modem control register */ u8 efr; /* Enhanced feature register */ u8 scr; /* Scratchpad register */ u8 tlr; /* Trigger level register */ u8 fcr; /* FIFO control register */ u8 ier; /* interrupt enable register */ u8 lcr; u8 rxfll; /* Received frame length register */ u8 rxflh; u8 txfll; u8 txflh; u8 acreg; u8 eblr;};struct uart_setparm { u8 lcr; u8 reg; u8 reg_data;}; struct uart_callback { /* tx/rx config - DMA/NonDMA mode */ int mode; void (*uart_tx_dma_callback)(int lch, u16 ch_status, void *data); void (*uart_rx_dma_callback)(int lch, u16 ch_status, void *data); int tx_buf_size; int rx_buf_size; /* ISR config */ void (*int_callback) (u8 , void*); char *dev_name; void *dev; int txrx_req_flag;}; /* Useful Macros *//* UART numbers */#define UART1 (0x0)#define UART2 (0x1)#define UART3 (0x2)#define MAX_UARTS UART3#define BASE_CLK (48000000)#define DISABLE 0#define ENABLE 1#define UART_MODE 0#define IRDA_MODE 1#define UART_AUTOBAUD_MODE 2#define CIR_MODE 3#define UART_DMA_MODE 0#define UART_NONDMA_MODE 1 #define IR_SIR_SPEED 115200#define IR_MIR_SPEED 1152000#define IR_FIR_SPEED 4000000#define UART_16X_SPEED 2304000#define UART_13X_SPEED 3686400#define SIP_PULSE 0x40#define BOF_1 0x01#define BOF_2 0x02 #define BOF_3 0x03/* MDR1 - Defines */#define UART_16X_MODE 0x00#define UART_SIR_MODE 0x01#define UART_16XAUTO_MODE 0x02 #define UART_13X_MODE 0x03 #define UART_MIR_MODE 0x04#define UART_FIR_MODE 0x05 #define UART_CIR_MODE 0x06#define UART_DISABLE 0x07#define MODE_SELECT_MASK ~(0x07)#define FIFO_SIZE 64 #define TXRX 0#define RX_ONLY 1#define TX_ONLY 2 #define LCR_MODE1 (0<<7)#define LCR_MODE2 (1<<7)#define LCR_MODE3 (0xbf)/* Function Templates */int omap24xx_uart_release(int uart_no);int omap24xx_uart_request(int uart_no, struct uart_callback*); int omap24xx_uart_stop(int uart_no);int omap24xx_uart_config(int uart_no, struct uart_config *uart_cfg);int omap24xx_uart_set_speed(int uart_no, int speed);int omap24xx_uart_get_speed(int uart_no, int *speed);int omap24xx_uart_set_parms(int uart_no, struct uart_setparm *uart_set);int omap24xx_uart_get_parms(int uart_no, u8 *param, u8 reg, u8 lcr_mode);int omap24xx_uart_start_rx(int uart_no, int size);int omap24xx_uart_start_tx(int uart_no, int size);int omap24xx_uart_interrupt(int uart_no, int enable);int omap24xx_uart_reset(int uart_no);int omap24xx_uart_stop_tx(int uart_no);int omap24xx_uart_stop_rx(int uart_no);int omap24xx_uart_rx(int uart_no, void *data, int *len);int omap24xx_uart_tx(int uart_no, void *data, int size );int console_detect(char *str);/* Useful Macros */#define UART_MODULE_BASE(uart_no) ( UART1 == uart_no ? IO_ADDRESS(OMAP_UART1_BASE) :\ ( UART2 == uart_no ? IO_ADDRESS(OMAP_UART2_BASE) :\ IO_ADDRESS(OMAP_UART3_BASE) ))#define UART_BASE(uart_no) (uart_no == UART1)?OMAP_UART1_BASE:(uart_no == UART2)?OMAP_UART2_BASE : OMAP_UART3_BASE/**************************************** * UARTIRDACIROCP ****************************************//**** Register Definitions */#define REG_RHR (0x0)#define REG_THR (0x0)#define REG_DLL (0x0)#define REG_IER (0x4)#define REG_DLH (0x4)#define REG_IIR (0x8)#define REG_FCR (0x8)#define REG_EFR (0x8)#define REG_LCR (0xC)#define REG_MCR (0x10)#define REG_XON1_ADDR1 (0x10)#define REG_LSR (0x14)#define REG_XON2_ADDR2 (0x14)#define REG_TCR (0x18)#define REG_MSR (0x18)#define REG_XOFF1 (0x18)#define REG_TLR (0x1C)#define REG_SPR (0x1C)#define REG_XOFF2 (0x1C)#define REG_MDR1 (0x20)#define REG_MDR2 (0x24)#define REG_SFLSR (0x28)#define REG_TXFLL (0x28)#define REG_RESUME (0x2C)#define REG_TXFLH (0x2C)#define REG_SFREGL (0x30)#define REG_RXFLL (0x30)#define REG_SFREGH (0x34)#define REG_RXFLH (0x34)#define REG_BLR (0x38)#define REG_UASR (0x38)#define REG_ACREG (0x3C)#define REG_SCR (0x40)#define REG_SSR (0x44)#define REG_EBLR (0x48)#define REG_MVR (0x50)#define REG_SYSC (0x54)#define REG_SYSS (0x58)#define REG_WER (0x5C)#define REG_CFPS (0x60)/**** BitField Definitions *//* DLL Fields */#define BIT_DLL_CLOCK_LSB (0x00)#define BIT_DLL_CLOCK_LSB_M (0xFF)/* RHR Fields */#define BIT_RHR_RHR (0x00)#define BIT_RHR_RHR_M (0xFF)/* THR Fields */#define BIT_THR_THR (0x00)#define BIT_THR_THR_M (0xFF)/* DLH Fields */#define BIT_DLH_CLOCK_MSB (0x00)#define BIT_DLH_CLOCK_MSB_M (0x3F)/* IER Fields */#define BIT_IER_RHR_IT (0x00)#define BIT_IER_RHR_IT_M (0x01)#define BIT_IER_THR_IT (0x01)#define BIT_IER_THR_IT_M (0x02)#define BIT_IER_LINE_STS_IT_U (0x02)#define BIT_IER_LINE_STS_IT_U_M (0x04)#define BIT_IER_LAST_RX_BYTE_IT (0x02)#define BIT_IER_LAST_RX_BYTE_IT_M (0x04)#define BIT_IER_RX_STOP_IT (0x02)#define BIT_IER_RX_STOP_IT_M (0x04)#define BIT_IER_MODEM_STS_IT (0x03)#define BIT_IER_MODEM_STS_IT_M (0x08)#define BIT_IER_RX_OVERRUN_IT (0x03)#define BIT_IER_RX_OVERRUN_IT_M (0x08)#define BIT_IER_SLEEP_MODE (0x04)#define BIT_IER_SLEEP_MODE_M (0x10)#define BIT_IER_STS_FIFO_TRIG_IT (0x04)#define BIT_IER_STS_FIFO_TRIG_IT_M (0x10)#define BIT_IER_XOFF_IT (0x05)#define BIT_IER_XOFF_IT_M (0x20)#define BIT_IER_TX_STATUS_IT (0x05)#define BIT_IER_TX_STATUS_IT_M (0x20)#define BIT_IER_RTS_IT (0x06)#define BIT_IER_RTS_IT_M (0x40)#define BIT_IER_LINE_STS_IT_I (0x06)#define BIT_IER_LINE_STS_IT_I_M (0x40)#define BIT_IER_CTS_IT (0x07)#define BIT_IER_CTS_IT_M (0x80)#define BIT_IER_EOF_IT (0x07)#define BIT_IER_EOF_IT_M (0x80)/* FCR Fields */#define BIT_FCR_FIFO_EN (0x00)#define BIT_FCR_FIFO_EN_M (0x01)/* IIR Fields */#define BIT_IIR_IT_PENDING (0x00)#define BIT_IIR_IT_PENDING_M (0x01)#define BIT_IIR_RHR_IT (0x00)#define BIT_IIR_RHR_IT_M (0x01)/* EFR Fields */#define BIT_EFR_SW_FLOW_CONTROL (0x00)#define BIT_EFR_SW_FLOW_CONTROL_M (0x0F)/* FCR Fields */#define BIT_FCR_RX_FIFO_CLEAR (0x01)#define BIT_FCR_RX_FIFO_CLEAR_M (0x02)/* IIR Fields */#define BIT_IIR_IT_TYPE (0x01)#define BIT_IIR_IT_TYPE_M (0x3E)#define BIT_IIR_THR_IT (0x01)#define BIT_IIR_THR_IT_M (0x02)/* FCR Fields */#define BIT_FCR_TX_FIFO_CLEAR (0x02)#define BIT_FCR_TX_FIFO_CLEAR_M (0x04)/* IIR Fields */#define BIT_IIR_RX_FIFO_LAST_BYTE_IT (0x02)#define BIT_IIR_RX_FIFO_LAST_BYTE_IT_M (0x04)#define BIT_IIR_RX_STOP_IT (0x02)#define BIT_IIR_RX_STOP_IT_M (0x04)/* FCR Fields */#define BIT_FCR_DMA_MODE (0x03)#define BIT_FCR_DMA_MODE_M (0x08)#define FCR_NO_DMA ~(0x08)/* IIR Fields */#define BIT_IIR_RX_OE_IT (0x03)#define BIT_IIR_RX_OE_IT_M (0x08)/* FCR Fields */#define BIT_FCR_TX_FIFO_TRIG (0x04)#define BIT_FCR_TX_FIFO_TRIG_M (0x30)#define FCR_TX_FIFO_TRIG_8 (0x00)#define FCR_TX_FIFO_TRIG_16 (0x10)#define FCR_TX_FIFO_TRIG_32 (0x20)#define FCR_TX_FIFO_TRIG_56 (0x30)/* IIR Fields */#define BIT_IIR_STS_FIFO_IT (0x04)#define BIT_IIR_STS_FIFO_IT_M (0x10)/* EFR Fields */#define BIT_EFR_ENHANCED_EN (0x04)#define BIT_EFR_ENHANCED_EN_M (0x10)/* IIR Fields */#define BIT_IIR_TX_STATUS_IT (0x05)#define BIT_IIR_TX_STATUS_IT_M (0x20)/* EFR Fields */#define BIT_EFR_SPECIAL_CHAR_DETECT (0x05)#define BIT_EFR_SPECIAL_CHAR_DETECT_M (0x20)/* FCR Fields */⌨️ 快捷键说明
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