prcm.h

omap3 linux 2.6 用nocc去除了冗余代码

#define R_VDD1_SR_CONTROL		0x00
#define R_VDD2_SR_CONTROL		0x01
#define T2_SMPS_UPDATE_DELAY		360	/* In uSec */

/* GPTimer wait delay */
#define GPTIMER_WAIT_DELAY		50	/* In usec */

#define PRCM_SAVE(x) prcm_sleep_save[PRCM_SLEEP_SAVE_##x] = x
#define PRCM_RESTORE(x) x = prcm_sleep_save[PRCM_SLEEP_SAVE_##x]
#define PRCM_SHOW(x) prcm_sleep_save[PRCM_SLEEP_SAVE_##x]

enum prcm_save_state {
	PRCM_SLEEP_SAVE_START = 0,
	PRCM_SLEEP_SAVE_INTC_MIR_0,
	PRCM_SLEEP_SAVE_INTC_MIR_1,
	PRCM_SLEEP_SAVE_INTC_MIR_2,
	PRCM_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQ,
	PRCM_SLEEP_SAVE_GPIO1_IRQENABLE1,
	PRCM_SLEEP_SAVE_GPIO1_WAKEUPENABLE,
	PRCM_SLEEP_SAVE_GPIO1_FALLINGDETECT,

	PRCM_SLEEP_SAVE_CM_CLKSEL2_PLL_IVA2,
	PRCM_SLEEP_SAVE_CM_SYSCONFIG,

	PRCM_SLEEP_SAVE_CM_CLKSEL_SGX,
	PRCM_SLEEP_SAVE_CM_CLKSEL_WKUP,

	PRCM_SLEEP_SAVE_CM_CLKSEL_DSS,

	PRCM_SLEEP_SAVE_CM_CLKSEL_CAM,
	PRCM_SLEEP_SAVE_CM_CLKSEL_PER,

	PRCM_SLEEP_SAVE_CM_CLKSEL1_EMU,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_EMU,

	PRCM_SLEEP_SAVE_CM_AUTOIDLE2_PLL,
	PRCM_SLEEP_SAVE_CM_CLKSEL5_PLL,
	PRCM_SLEEP_SAVE_CM_POLCTRL,

	PRCM_SLEEP_SAVE_CM_FCLKEN_IVA2,
	PRCM_SLEEP_SAVE_CM_FCLKEN1_CORE,
	PRCM_SLEEP_SAVE_CM_FCLKEN3_CORE,
	PRCM_SLEEP_SAVE_CM_FCLKEN_SGX,
	PRCM_SLEEP_SAVE_CM_FCLKEN_WKUP,
	PRCM_SLEEP_SAVE_CM_FCLKEN_DSS,
	PRCM_SLEEP_SAVE_CM_FCLKEN_CAM,
	PRCM_SLEEP_SAVE_CM_FCLKEN_PER,
	PRCM_SLEEP_SAVE_CM_FCLKEN_USBHOST,
	PRCM_SLEEP_SAVE_CM_ICLKEN1_CORE,
	PRCM_SLEEP_SAVE_CM_ICLKEN2_CORE,
	PRCM_SLEEP_SAVE_CM_ICLKEN3_CORE,
	PRCM_SLEEP_SAVE_CM_ICLKEN_SGX,
	PRCM_SLEEP_SAVE_CM_ICLKEN_WKUP,
	PRCM_SLEEP_SAVE_CM_ICLKEN_DSS,
	PRCM_SLEEP_SAVE_CM_ICLKEN_CAM,
	PRCM_SLEEP_SAVE_CM_ICLKEN_PER,
	PRCM_SLEEP_SAVE_CM_ICLKEN_USBHOST,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL_IVA2,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL_MPU,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL,

	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_IVA2,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_SGX,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_DSS,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_CAM,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_PER,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_NEON,
	PRCM_SLEEP_SAVE_CM_CLKSTCTRL_USBHOST,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_DSS,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_CAM,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_PER,
	PRCM_SLEEP_SAVE_CM_AUTOIDLE_USBHOST,
	PRCM_SLEEP_SAVE_CM_SLEEPDEP_SGX,
	PRCM_SLEEP_SAVE_CM_SLEEPDEP_DSS,
	PRCM_SLEEP_SAVE_CM_SLEEPDEP_CAM,
	PRCM_SLEEP_SAVE_CM_SLEEPDEP_PER,
	PRCM_SLEEP_SAVE_CM_SLEEPDEP_USBHOST,
	PRCM_SLEEP_SAVE_CM_CLKOUT_CTRL,
	PRCM_SLEEP_SAVE_PRM_CLKOUT_CTRL,

	PRCM_SLEEP_SAVE_PM_WKDEP_IVA2,
	PRCM_SLEEP_SAVE_PM_WKDEP_MPU,
	PRCM_SLEEP_SAVE_PM_WKDEP_SGX,
	PRCM_SLEEP_SAVE_PM_WKDEP_DSS,
	PRCM_SLEEP_SAVE_PM_WKDEP_CAM,
	PRCM_SLEEP_SAVE_PM_WKDEP_PER,
	PRCM_SLEEP_SAVE_PM_WKDEP_NEON,
	PRCM_SLEEP_SAVE_PM_WKDEP_USBHOST,
	PRCM_SLEEP_SAVE_PM_MPUGRPSEL1_CORE,
	PRCM_SLEEP_SAVE_PM_IVA2GRPSEL1_CORE,
	PRCM_SLEEP_SAVE_PM_IVA2GRPSEL3_CORE,
	PRCM_SLEEP_SAVE_PM_MPUGRPSEL3_CORE,
	PRCM_SLEEP_SAVE_PM_MPUGRPSEL_WKUP,
	PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_WKUP,
	PRCM_SLEEP_SAVE_PM_MPUGRPSEL_PER,
	PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_PER,
	PRCM_SLEEP_SAVE_PM_MPUGRPSEL_USBHOST,
	PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_USBHOST,
	PRCM_SLEEP_SAVE_PM_WKEN_WKUP,

	PRCM_SLEEP_SAVE_SIZE
};


extern void omap_sram_idle(void);
extern void omap3_configure_core_dpll(u32 tar_m, u32 tar_n, u32 tar_freqsel,
				u32 tar_m2);

/* Structure to save interrupt controller context */
struct int_controller_context {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[96];
	u32 mir_0;
	u32 mir_1;
	u32 mir_2;
};

/* Structure to save control module context */
struct control_module_context {
	u32 sysconfig;
	u32 devconf0;
	u32 mem_dftrw0;
	u32 mem_dftrw1;
	u32 msuspendmux_0;
	u32 msuspendmux_1;
	u32 msuspendmux_2;
	u32 msuspendmux_3;
	u32 msuspendmux_4;
	u32 msuspendmux_5;
	u32 sec_ctrl;
	u32 devconf1;
	u32 csirxfe;
	u32 iva2_bootaddr;
	u32 iva2_bootmod;
	u32 debobs_0;
	u32 debobs_1;
	u32 debobs_2;
	u32 debobs_3;
	u32 debobs_4;
	u32 debobs_5;
	u32 debobs_6;
	u32 debobs_7;
	u32 debobs_8;
	u32 prog_io0;
	u32 prog_io1;
	u32 dss_dpll_spreading;
	u32 core_dpll_spreading;
	u32 per_dpll_spreading;
	u32 usbhost_dpll_spreading;
	u32 pbias_lite;
	u32 temp_sensor;
	u32 sramldo4;
	u32 sramldo5;
	u32 csi;
};

/* Structure to save gpmc cs context */
struct gpmc_cs_context {
	int cs_valid;
	u32 config1;
	u32 config2;
	u32 config3;
	u32 config4;
	u32 config5;
	u32 config6;
	u32 config7;
};

/* Structure to save gpmc context */
struct gpmc_context {
	u32 sysconfig;
	u32 irqenable;
	u32 timeout_ctrl;
	u32 config;
	u32 prefetch_config1;
	u32 prefetch_config2;
	u32 prefetch_control;
	struct gpmc_cs_context cs0_context;
	struct gpmc_cs_context cs1_context;
	struct gpmc_cs_context cs2_context;
	struct gpmc_cs_context cs3_context;
	struct gpmc_cs_context cs4_context;
	struct gpmc_cs_context cs5_context;
	struct gpmc_cs_context cs6_context;
	struct gpmc_cs_context cs7_context;
};

/* Register Types */
enum regtype {
	REG_FCLKEN,
	REG_ICLKEN,
	REG_IDLEST,
	REG_AUTOIDLE,
	REG_WKEN,
	REG_WKST,
	REG_CLKSTCTRL,
	REG_CLKSTST,
	REG_PWSTCTRL,
	REG_PWSTST,
	REG_PREPWSTST,
	REG_CLK_SRC,
	REG_RSTST,
	PRCM_REG_TYPES,
};

enum dpll_regtype {
	REG_CLKEN_PLL,
	REG_AUTOIDLE_PLL,
	REG_CLKSEL1_PLL,
	REG_IDLEST_PLL,
	REG_M2_DIV_PLL,
	REG_M2X2_DIV_PLL,
	REG_M3_DIV_PLL,
	REG_M4_DIV_PLL,
	REG_M5_DIV_PLL,
	REG_M6_DIV_PLL,
	PRCM_DPLL_REG_TYPES,
};

struct dpll_param {
	u32 dpll_m;
	u32 dpll_n;
	u32 dpll_freqsel;
	u32 dpll_m2;
};

struct system_power_state {
	u32 iva2_state;
	u32 gfx_state;
	u32 dss_state;
	u32 cam_state;
	u32 per_state;
	u32 neon_state;
	u32 usbhost_state;
	u32 mpu_state;
	u32 core_state;
};

/* Offset of MX registers in the pll_register array*/
#define MX_ARRAY_OFFSET REG_M2_DIV_PLL

/* Structure to store the attributes of register */
struct reg_def {
	u32 valid_bits;
	volatile u32 *reg_addr;
};

struct sysconf_reg {
	u32 device_id;
	volatile u32 *reg_addr;
	};
/* Structure to store attributes of registers in a domain */
struct domain_registers {
	struct reg_def regdef[PRCM_REG_TYPES];
};

/* Structure to store DPLL information */
struct dpll_registers {
	struct reg_def regdef[PRCM_DPLL_REG_TYPES];
};

/* Structure for mpu, core and VDD states */
/* This structure will be used in OS Idle code */
struct mpu_core_vdd_state {
	u32 mpu_state;
	u32 core_state;
	u32 vdd_state;
};

/* SDRC/GPMC params for DVFS */

struct sdrc_config {
	u32 sdrc_rfr_ctrl;
	u32 sdrc_actim_ctrla;
	u32 sdrc_actim_ctrlb;
};

struct gpmc_config {
	u32 gpmc_config2;
	u32 gpmc_config3;
	u32 gpmc_config4;
	u32 gpmc_config5;
	u32 gpmc_config6;
};

#define no_sdrc_cs 2
#define no_gpmc_cs 4

struct dvfs_config {
	struct sdrc_config sdrc_cfg[no_sdrc_cs];
	struct gpmc_config gpmc_cfg[no_gpmc_cs];
};

extern int prcm_clock_control(u32 deviceid, u8 clk_type, u8 control,
			      u8 checkaccessibility);
extern int prcm_is_device_accessible(u32 deviceid, u8 * result);
extern int prcm_interface_clock_autoidle(u32 deviceid, u8 control);
extern int prcm_wakeup_event_control(u32 deviceid, u8 control);

/* DPLL control APIs */
extern int prcm_enable_dpll(u32 dpll);
extern int prcm_configure_dpll(u32 dpll, u32 mult, u8 div, u8 freq_sel);
extern int prcm_put_dpll_in_bypass(u32 dpll, u32 bypass_mode);
extern int prcm_dpll_clock_auto_control(u32 dpll, u32 setting);
extern int prcm_get_dpll_mn_output(u32 dpll, u32 * mn_output);
extern int prcm_get_dpll_rate(u32 dpll, u32 * rate);
extern int prcm_configure_dpll_divider(u32 dpll, u32 setting);

/* Other APIs*/
extern int prcm_get_power_domain_state(u32 domainid, u8 * result);
extern int prcm_get_pre_power_domain_state(u32 domainid, u8 * result);
extern int prcm_is_clock_domain_active(u32 domainid, u8 * result);
extern int prcm_set_clock_domain_state(u32 domainid, u8 new_state,
						u8 check_state);
extern int prcm_set_power_domain_state(u32 domainid, u8 new_state, u8 mode);
extern int prcm_get_devices_not_idle(u32 domainid, u32 * result);
extern int prcm_get_initiators_not_standby(u32 domainid, u32 * result);
extern int prcm_get_domain_interface_clocks(u32 domainid, u32 * result);
extern int prcm_get_domain_functional_clocks(u32 domainid, u32 * result);
extern int prcm_set_domain_interface_clocks(u32 domainid, u32 setmask);
extern int prcm_set_domain_functional_clocks(u32 domainid, u32 setmask);
extern int prcm_get_crystal_rate(void);
extern int prcm_get_system_clock_speed(void);
extern int prcm_select_system_clock_divider(u32 setting);
extern int prcm_control_external_output_clock1(u32 control);
extern int prcm_control_external_output_clock2(u32 control);
extern int prcm_select_external_output_clock2_divider(u32 setting);
extern int prcm_select_external_output_clock2_source(u32 setting);
extern int prcm_clksel_get_divider(u32 clk, u32 * div);
extern int prcm_clksel_set_divider(u32 clk, u32 div);
extern int prcm_get_processor_speed(u32 domainid, u32 * processor_speed);
extern int prcm_clksel_round_rate(u32 clk, u32 parent_rate, u32 target_rate,
				  u32 * newdiv);
extern int prcm_clk_set_source(u32 clk_id, u32 parent_id);
extern int prcm_clk_get_source(u32 clk_id, u32 * parent_id);
extern int prcm_set_power_configuration(u32 domainid, u8 idlemode,
					u8 standbymode, u8 autoidleenable);
extern int prcm_set_wkup_dependency(u32 domainid, u32 wkup_dep);
extern int prcm_set_sleep_dependency(u32 domainid, u32 sleep_dep);
extern int prcm_clear_wkup_dependency(u32 domainid, u32 wkup_dep);
extern int prcm_clear_sleep_dependency(u32 domainid, u32 sleep_dep);
extern int prcm_set_mpu_domain_state(u32 mpu_dom_state);
extern int prcm_set_core_domain_state(u32 core_dom_state);
extern void prcm_printreg(u32 domainid);

extern int prcm_init(void);
extern int prcm_set_domain_power_configuration(u32 domainid, u8 idlemode,
					u8 standbymode, u8 autoidleenable);
extern int prcm_set_device_power_configuration(u32 deviceid, u8 idlemode,
					u8 standbymode, u8 autoidleenable);
extern int get_dpll_m_n(u32 dpll_id, u32 * mult, u32 * div);
/* Level 2 PRCM APIs */
extern int prcm_do_frequency_scaling(u32 target_opp, u32 current_opp);
extern int prcm_do_voltage_scaling(u32 target_opp, u32 current_opp);
extern int prcm_force_power_domain_state(u32 domain, u8 state);
extern int prcm_set_chip_power_mode(struct system_power_state *target_state,
							u32 wakeup_source);
extern void omap_dma_global_context_restore(void);
extern void omap_dma_global_context_save(void);
extern int prcm_lock_iva_dpll(u32 target_opp);
extern void omap_udelay(u32 delay);
void clear_domain_reset_status(void);
u32 omap_prcm_get_reset_sources(void);

extern int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);