prcm.h

omap3 linux 2.6 用nocc去除了冗余代码

			ID_CLK_NO(0x6) | ID_DEV_BIT_POS(0x1))
#define PRCM_3D_CONSTRAINT	(ID_OMAP(AT_3430) |\
				OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				ID_DOMAIN(DOM_SGX))

/* Devices in WKUP registers */
#define PRCM_GPT1	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
						| ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_WKUP) | \
				ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x0))
#define PRCM_GPT12	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x1))
#define PRCM_32KSYNC	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x2))
#define PRCM_GPIO1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x3))
#define PRCM_WDT1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x4))
#define PRCM_WDT2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x5))
#define PRCM_SR1	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x6))
#define PRCM_SR2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				| ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x7))
#define PRCM_USIM	(ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_CLK_DIV |\
				ID_CLK_SRC)) | ID_DEV_TYPE(TARGET) |\
				ID_DOMAIN(DOM_WKUP)\
				| ID_DEV_BIT_POS(0x9) | ID_CLK_NO(0xA))

/* Devices in IVA registers */
#define PRCM_IVA2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
					| ID_DOMAIN(DOM_IVA2) | ID_DEV_BIT_POS(0x0))
#define PRCM_IVA2_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_IVA2))
/* Devices in DSS registers */
#define PRCM_DSS	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_DPLL_OP)) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x0) | \
				ID_DPLL_DIV(DPLL_M4X2) | ID_DPLL_NO(DPLL4_PER) )
#define PRCM_DSS2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x1))
#define PRCM_TVOUT	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC)) | \
				ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x2))
#define PRCM_DISPC	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INIT_TAR) \
				| ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x1))
#define PRCM_RFBI	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INITIATOR) \
				| ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x2))

#define PRCM_DSS_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_DSS))

/* Devices in CAM Domain */
#define PRCM_CAM	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_DPLL_OP)) | ID_DEV_TYPE(INITIATOR)\
			 	| ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x0) |\
				 ID_DPLL_DIV(DPLL_M5X2) | ID_DPLL_NO(DPLL4_PER))

#define PRCM_CSI2	(ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_DPLL_OP)) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x1))

#define PRCM_CSIA	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INIT_TAR)\
				 | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x1))
#define PRCM_CSIB	(ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INIT_TAR)\
				 | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x2))
#define PRCM_MMU        (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INIT_TAR)\
                                 | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x3))
#define PRCM_ISP_CTRL   (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) | ID_DEV_TYPE(INIT_TAR)\
                                 | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x4))
#define PRCM_CAM_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_CAM))

/* Devices in PER Domain */
#define PRCM_MCBSP2	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0x0))
#define PRCM_MCBSP3	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x1))
#define PRCM_MCBSP4	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x2))
#define PRCM_GPT2	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x3))
#define PRCM_GPT3	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x1) | ID_DEV_BIT_POS(0x4))
#define PRCM_GPT4	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x5))
#define PRCM_GPT5	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x3) | ID_DEV_BIT_POS(0x6))
#define PRCM_GPT6	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x4) | ID_DEV_BIT_POS(0x7))
#define PRCM_GPT7	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x5) | ID_DEV_BIT_POS(0x8))
#define PRCM_GPT8	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0x9))
#define PRCM_GPT9	(ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
				| ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
				ID_CLK_SRC_BIT_POS(0x7) | ID_DEV_BIT_POS(0xA))
#define PRCM_UART3	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xB))
#define PRCM_WDT3	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xC))
#define PRCM_GPIO2	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xD))
#define PRCM_GPIO3	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xE))
#define PRCM_GPIO4	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xF))
#define PRCM_GPIO5	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0x10))
#define PRCM_GPIO6	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
				|ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0x11))
#define PRCM_PER_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_PER))

/* Devices in NEON Domain */
#define PRCM_NEON	(ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_NEON) | ID_DEV_BIT_POS(0x0))
#define PRCM_NEON_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_NEON))

/* Devices in USBHOST Domain */
#define PRCM_USBHOST1	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(INITIATOR)\
				| ID_DOMAIN(DOM_USBHOST) | ID_DEV_BIT_POS(0x0))
#define PRCM_USBHOST2	(ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_DPLL_OP))\
				| ID_DEV_TYPE(INITIATOR) | ID_DOMAIN(DOM_USBHOST)\
				| ID_DEV_BIT_POS(0x1)| ID_DPLL_DIV(DPLL_M2)\
				| ID_DPLL_NO(DPLL5_PER2))
#define PRCM_USBHOST_CONSTRAINT	(ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
				 ID_DOMAIN(DOM_USBHOST))

/* DPLL ID's */
#define PRCM_DPLL1_M2X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL1_MPU))
#define PRCM_DPLL2_M2X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL2_IVA2))
#define PRCM_DPLL3_M2_CLK 	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2) | ID_DPLL_NO(DPLL3_CORE))
#define PRCM_DPLL3_M2X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL3_CORE))
#define PRCM_DPLL3_M3X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M3X2) | ID_DPLL_NO(DPLL3_CORE))
#define PRCM_DPLL4_M2X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL4_PER))
#define PRCM_DPLL4_M3X2_CLK 	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M3X2) | ID_DPLL_NO(DPLL4_PER))
#define PRCM_DPLL4_M6X2_CLK	(ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M6X2) | ID_DPLL_NO(DPLL4_PER))
#define PRCM_DPLL5_M2_CLK	(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DPLL_OP)\
				| ID_DPLL_DIV(DPLL_M2) | ID_DPLL_NO(DPLL5_PER2))

/* CLK ID's */
#define PRCM_L3_ICLK 		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
							ID_CLK_NO(0x1))
#define PRCM_L4_ICLK 		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
							ID_CLK_NO(0x2))
#define PRCM_RM_ICLK 		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
							ID_CLK_NO(0x3))
#define PRCM_SYS_CLKOUT2 	(ID_OMAP(AT_3430) | ID_TYPE((ID_CLK_DIV  | ID_CLK_SRC))\
							| ID_CLK_NO(0x5))

#define PRCM_DPLL1_FCLK		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
							| ID_CLK_NO(0x8))
#define PRCM_DPLL2_FCLK		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
							| ID_CLK_NO(0x9))
#define PRCM_96M_CLK		(ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_CLK_SRC)\
							| ID_CLK_SRC_BIT_POS(0x6))
#define PRCM_NO_OF_CLKS		0xA
/* func_48m_fclk and func_12m_fclk have dividers */
/*but they are fixed dividers.*/
/*So these are not included in the array */
#define PRCM_48M_FCLK 		(ID_OMAP(AT_3430) | ID_TYPE((ID_CLK_DIV\
							| ID_CLK_SRC)) | ID_CLK_NO(0xB))
#define PRCM_12M_FCLK 		(ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
							| ID_CLK_NO(0xE))
/* Clock IDs for parent clocks */
#define PRCM_SYS_ALT_CLK	(OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
							| ID_CLK_NO(0xF))
#define PRCM_SYS_CLK		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
							| ID_CLK_NO(0x10))
#define PRCM_SYS_32K_CLK	(OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
							| ID_CLK_NO(0x11))
#define PRCM_EXT_MCBSP_CLK	(OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
							| ID_CLK_NO(0x12))
#define PRCM_SYS_CLKOUT1	(OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
							| ID_CLK_NO(0x13))
/* VDD1 OPPs */
#define PRCM_VDD1_OPP1		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD1)\
							| ID_OPP_NO(0x1))
#define PRCM_VDD1_OPP2		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD1)\
							| ID_OPP_NO(0x2))
#define PRCM_VDD1_OPP3		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD1)\
							| ID_OPP_NO(0x3))
#define PRCM_VDD1_OPP4		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD1)\
							| ID_OPP_NO(0x4))
#define PRCM_VDD1_OPP5		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD1)\
							| ID_OPP_NO(0x5))
#define PRCM_NO_VDD1_OPPS	5

/* VDD2 OPPs */
#define PRCM_VDD2_OPP1		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD2)\
							| ID_OPP_NO(0x1))
#define PRCM_VDD2_OPP2		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD2)\
							| ID_OPP_NO(0x2))
#define PRCM_VDD2_OPP3		(OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) | ID_VDD(PRCM_VDD2)\
							| ID_OPP_NO(0x3))
#define PRCM_NO_VDD2_OPPS	3

/* OPP and Frequency Constraints */
#define PRCM_VDD1_CONSTRAINT 	(ID_OMAP(AT_3430) | \
				OTHER_ID_TYPE(ID_CONSTRAINT_OPP) | 0x1)
#define PRCM_VDD2_CONSTRAINT 	(ID_OMAP(AT_3430) | \
				OTHER_ID_TYPE(ID_CONSTRAINT_OPP) | 0x2)
#define PRCM_ARMFREQ_CONSTRAINT (ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_FREQ) | 0x3)
#define PRCM_DSPFREQ_CONSTRAINT (ID_OMAP(AT_3430) | \
				 OTHER_ID_TYPE(ID_CONSTRAINT_FREQ) | 0x4)

/* Mpu power domain states */
#define PRCM_MPU_ACTIVE		(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x0)
#define PRCM_MPU_INACTIVE	(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x1)
#define PRCM_MPU_CSWR_L2RET	(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x3)
#define PRCM_MPU_CSWR_L2OFF	(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x7)
#define PRCM_MPU_OSWR_L2RET	(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0xF)
#define PRCM_MPU_OSWR_L2OFF	(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x1F)
#define PRCM_MPU_OFF		(OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x3F)

/* Core power domain states */
#define PRCM_CORE_ACTIVE	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x0)
#define PRCM_CORE_INACTIVE	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1)
#define PRCM_CORE_CSWR_MEMRET	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3)
#define PRCM_CORE_CSWR_MEM1OFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x7)
#define PRCM_CORE_CSWR_MEM2OFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0xF)
#define PRCM_CORE_CSWR_MEMOFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1F)
#define PRCM_CORE_OSWR_MEMRET	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3F)
#define PRCM_CORE_OSWR_MEM1OFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x7F)
#define PRCM_CORE_OSWR_MEM2OFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0xFF)
#define PRCM_CORE_OSWR_MEMOFF	(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1FF)
#define PRCM_CORE_OFF		(OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3FF)

/* Memory and Logic resources */
#define PRCM_MPU_L2CACHEON	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_MPU) | 0x1)
#define PRCM_MPU_L2CACHERET	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_MPU) | 0x2)
#define PRCM_MPU_LOGICL1CACHERET	(OTHER_ID_TYPE(ID_LOGIC_RES) | \
						ID_DOMAIN(DOM_MPU) | 0x3)

#define PRCM_CORE_MEM2ON	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x1)
#define PRCM_CORE_MEM1ON	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x2)
#define PRCM_CORE_MEM2RET	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x3)
#define PRCM_CORE_MEM1RET	(OTHER_ID_TYPE(ID_MEMORY_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x4)
#define PRCM_CORE_LOGICRET	(OTHER_ID_TYPE(ID_LOGIC_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x5)
#define  PRCM_CORE_MEMORYCHANGE (OTHER_ID_TYPE(ID_LOGIC_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x6)
#define  PRCM_CORE_POWERSTATE   (OTHER_ID_TYPE(ID_LOGIC_RES) | \
						ID_DOMAIN(DOM_CORE1) | 0x7)

#define PRCM_PER_LOGICRET	(OTHER_ID_TYPE(ID_LOGIC_RES) | \
						ID_DOMAIN(DOM_PER) | 0x1)

/* VDD1 and VDD2 sleep states */
#define PRCM_VDD_ACTIVE		1
#define PRCM_VDD_RET		2
#define PRCM_VDD_OFF		3

#define PRCM_WAKEUP_T2_KEYPAD	0x1
#define PRCM_WAKEUP_TOUCHSCREEN	0x2
#define PRCM_WAKEUP_UART1	0x4

/* PRM_VC_SMPS_SA */
#define PRM_VC_SMPS_SA1_SHIFT	16
#define PRM_VC_SMPS_SA1_MASK	(0x7F << 16)
#define PRM_VC_SMPS_SA0_SHIFT	0
#define PRM_VC_SMPS_SA0_MASK	(0x7F << 16)

/* PRM_VC_SMPS_VOL_RA */
#define PRM_VC_SMPS_VOLRA1_SHIFT	16
#define PRM_VC_SMPS_VOLRA1_MASK		(0xFF << 16)
#define PRM_VC_SMPS_VOLRA0_SHIFT	0
#define PRM_VC_SMPS_VOLRA0_MASK		(0xFF << 0)

/* PRM_VC_SMPS_CMD_RA */
#define PRM_VC_SMPS_CMDRA1_SHIFT	16
#define PRM_VC_SMPS_CMDRA1_MASK		(0xFF << 16)
#define PRM_VC_SMPS_CMDRA0_SHIFT	0
#define PRM_VC_SMPS_CMDRA0_MASK		(0xFF << 0)

/* PRM_VC_CMD_VAL_0 specific bits */
#define PRM_VC_CMD_VAL0_ON		0x30
#define PRM_VC_CMD_VAL0_ONLP		0x18
#define PRM_VC_CMD_VAL0_RET		0x18
#define PRM_VC_CMD_VAL0_OFF		0x18

/* PRM_VC_CMD_VAL_1 specific bits */
#define PRM_VC_CMD_VAL1_ON		0x2C
#define PRM_VC_CMD_VAL1_ONLP		0x18
#define PRM_VC_CMD_VAL1_RET		0x18
#define PRM_VC_CMD_VAL1_OFF		0x18

#define PRM_VC_CMD_ON_SHIFT		24
#define PRM_VC_CMD_ON_MASK		(0xFF << 24)
#define PRM_VC_CMD_ONLP_SHIFT		16
#define PRM_VC_CMD_ONLP_MASK		(0xFF << 16)
#define PRM_VC_CMD_RET_SHIFT		8
#define PRM_VC_CMD_RET_MASK		(0xFF << 8)
#define PRM_VC_CMD_OFF_SHIFT		0
#define PRM_VC_CMD_OFF_MASK		(0xFF << 0)

/* PRM_VC_BYPASS_VAL */
#define PRM_VC_BYPASS_VALID		(0x1 << 24)
#define PRM_VC_BYPASS_DATA_SHIFT	16
#define PRM_VC_BYPASS_DATA_MASK		(0xFF << 16)
#define PRM_VC_BYPASS_REGADDR_SHIFT	8
#define PRM_VC_BYPASS_REGADDR_MASK	(0xFF << 8)
#define PRM_VC_BYPASS_SLAVEADDR_SHIFT	0
#define PRM_VC_BYPASS_SLAVEADDR_MASK	(0x7F << 0)

/* PRM_VC_CH_CONF */
#define PRM_VC_CH_CONF_CMD1		(0x1 << 20)
#define PRM_VC_CH_CONF_RAV1		(0x1 << 17)

/* PRM_VC_I2C_CFG */
#define PRM_VC_I2C_CFG_MCODE		0x0
#define PRM_VC_I2C_CFG_HSEN		(0x1 << 3)
#define PRM_VC_I2C_CFG_SREN		(0x1 << 4)
#define PRM_VC_I2C_CFG_HSMASTER		(0x1 << 5)

/* PRM_VOLTCTRL */
#define PRM_VOLTCTRL_AUTO_SLEEP		0x1
#define PRM_VOLTCTRL_AUTO_RET		0x2
#define PRM_VOLTCTRL_AUTO_OFF		0x4
#define PRM_VOLTCTRL_SEL_OFF		0x8
#define PRM_VOLTCTRL_SEL_VMODE		0x10

/* Constants to define setup durations */
#define PRM_CLKSETUP_DURATION		0xFF
#define PRM_VOLTSETUP_TIME2		0xFFF
#define PRM_VOLTSETUP_TIME1		0xFFF
#define PRM_VOLTOFFSET_DURATION		0xFF
#define PRM_VOLTSETUP2_DURATION		0xFF

/* PRM_VOLTSETUP1 */
#define PRM_VOLTSETUP_TIME2_OFFSET	16
#define PRM_VOLTSETUP_TIME1_OFFSET	0

/* PRM_POLCTRL */
#define PRM_POL_SYSOFFMODE		0x8

/* PRM_IRQENABLE_MPU */
#define PRM_VC_TIMEOUTERR_EN		(0x1 << 24)
#define PRM_VC_RAERR_EN			(0x1 << 23)
#define PRM_VC_SAERR_EN			(0x1 << 22)

/* PRM_IRQSTATUS_MPU */
#define PRM_VC_TIMEOUTERR_ST		(0x1 << 24)
#define PRM_VC_RAERR_ST			(0x1 << 23)
#define PRM_VC_SAERR_ST			(0x1 << 22)

/* T2 SMART REFLEX */
#define R_SRI2C_SLAVE_ADDR		0x12